mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 04:32:44 +01:00
e1e1463f1c
PAC/BTI-related codegen in the AArch64 backend is controlled by a set of LLVM IR function attributes, added to the function by Clang, based on command-line options and GCC-style function attributes. However, functions, generated in the LLVM middle end (for example, asan.module.ctor or __llvm_gcov_write_out) do not get any attributes and the backend incorrectly does not do any PAC/BTI code generation. This patch record the default state of PAC/BTI codegen in a set of LLVM IR module-level attributes, based on command-line options: * "sign-return-address", with non-zero value means generate code to sign return addresses (PAC-RET), zero value means disable PAC-RET. * "sign-return-address-all", with non-zero value means enable PAC-RET for all functions, zero value means enable PAC-RET only for functions, which spill LR. * "sign-return-address-with-bkey", with non-zero value means use B-key for signing, zero value mean use A-key. This set of attributes are always added for AArch64 targets (as opposed, for example, to interpreting a missing attribute as having a value 0) in order to be able to check for conflicts when combining module attributed during LTO. Module-level attributes are overridden by function level attributes. All the decision making about whether to not to generate PAC and/or BTI code is factored out into AArch64FunctionInfo, there shouldn't be any places left, other than AArch64FunctionInfo, which directly examine PAC/BTI attributes, except AArch64AsmPrinter.cpp, which is/will-be handled by a separate patch. Differential Revision: https://reviews.llvm.org/D85649
76 lines
2.6 KiB
YAML
76 lines
2.6 KiB
YAML
# RUN: llc -mtriple=aarch64--- -run-pass=machine-outliner \
|
|
# RUN: -verify-machineinstrs %s -o - | FileCheck %s
|
|
|
|
# CHECK-NOT: OUTLINED_FUNCTION
|
|
|
|
--- |
|
|
define void @f1() #0 { ret void }
|
|
define void @f2() #0 { ret void }
|
|
define void @f3() #0 { ret void }
|
|
define void @f4() #0 { ret void }
|
|
attributes #0 = { minsize noredzone "branch-target-enforcement"="true" }
|
|
...
|
|
---
|
|
name: f1
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
|
|
$x20, $x19 = LDPXi $sp, 11
|
|
$x20, $x19 = LDPXi $sp, 12
|
|
$x20, $x19 = LDPXi $sp, 13
|
|
$x20, $x19 = LDPXi $sp, 14
|
|
$x20, $x19 = LDPXi $sp, 18
|
|
$x20, $x19 = LDPXi $sp, 19
|
|
$x20, $x19 = LDPXi $sp, 20
|
|
$x20, $x19 = LDPXi $sp, 21
|
|
BLR $x20, implicit $sp
|
|
bb.2:
|
|
liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
|
|
RET undef $lr
|
|
...
|
|
---
|
|
name: f2
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
|
|
$x20, $x19 = LDPXi $sp, 11
|
|
$x20, $x19 = LDPXi $sp, 12
|
|
$x20, $x19 = LDPXi $sp, 13
|
|
$x20, $x19 = LDPXi $sp, 14
|
|
$x20, $x19 = LDPXi $sp, 18
|
|
$x20, $x19 = LDPXi $sp, 19
|
|
$x20, $x19 = LDPXi $sp, 20
|
|
$x20, $x19 = LDPXi $sp, 21
|
|
BLR $x20, implicit $sp
|
|
bb.2:
|
|
liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
|
|
RET undef $lr
|
|
...
|
|
---
|
|
name: f3
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
|
|
$x20, $x19 = LDPXi $sp, 11
|
|
$x20, $x19 = LDPXi $sp, 12
|
|
$x20, $x19 = LDPXi $sp, 13
|
|
$x20, $x19 = LDPXi $sp, 14
|
|
$x20, $x19 = LDPXi $sp, 18
|
|
$x20, $x19 = LDPXi $sp, 19
|
|
$x20, $x19 = LDPXi $sp, 20
|
|
$x20, $x19 = LDPXi $sp, 21
|
|
BLR $x20, implicit $sp
|
|
bb.2:
|
|
liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
|
|
RET undef $lr
|
|
...
|
|
---
|
|
name: f4
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
RET undef $lr
|