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https://github.com/RPCS3/llvm-mirror.git
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4bfea803ed
After D98856 these tests will by default break (fatal_error) if any of the wrong interfaces are used, so there's no longer a need to have a RUN line that checks for a warning message emitted by the compiler.
234 lines
8.6 KiB
LLVM
234 lines
8.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SELDAG %s
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; RUN: llc -verify-machineinstrs -O0 < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-FASTISEL %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; VECTOR_REVERSE - PPR
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;
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define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) #0 {
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; CHECK-LABEL: reverse_nxv2i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev p0.d, p0.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1> %a)
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ret <vscale x 2 x i1> %res
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}
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define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) #0 {
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; CHECK-LABEL: reverse_nxv4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev p0.s, p0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1> %a)
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ret <vscale x 4 x i1> %res
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}
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define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) #0 {
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; CHECK-LABEL: reverse_nxv8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev p0.h, p0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1> %a)
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ret <vscale x 8 x i1> %res
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}
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define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) #0 {
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; CHECK-LABEL: reverse_nxv16i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev p0.b, p0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1> %a)
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ret <vscale x 16 x i1> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) #0 {
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; CHECK-LABEL: reverse_nxv32i1:
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; CHECK-SELDAG: // %bb.0:
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; CHECK-SELDAG-NEXT: rev p2.b, p1.b
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; CHECK-SELDAG-NEXT: rev p1.b, p0.b
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; CHECK-SELDAG-NEXT: mov p0.b, p2.b
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; CHECK-SELDAG-NEXT: ret
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; CHECK-FASTISEL: // %bb.0:
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; CHECK-FASTISEL-NEXT: str x29, [sp, #-16]
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; CHECK-FASTISEL-NEXT: addvl sp, sp, #-1
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; CHECK-FASTISEL-NEXT: str p1, [sp, #7, mul vl]
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; CHECK-FASTISEL-NEXT: mov p1.b, p0.b
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; CHECK-FASTISEL-NEXT: ldr p0, [sp, #7, mul vl]
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; CHECK-FASTISEL-NEXT: rev p0.b, p0.b
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; CHECK-FASTISEL-NEXT: rev p1.b, p1.b
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; CHECK-FASTISEL-NEXT: addvl sp, sp, #1
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; CHECK-FASTISEL-NEXT: ldr x29, [sp], #16
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; CHECK-FASTISEL-NEXT: ret
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%res = call <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1> %a)
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ret <vscale x 32 x i1> %res
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}
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;
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; VECTOR_REVERSE - ZPR
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;
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define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: reverse_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev z0.b, z0.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8> %a)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @reverse_nxv8i16(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: reverse_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev z0.h, z0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16> %a)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: reverse_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev z0.s, z0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) #0 {
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; CHECK-LABEL: reverse_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev z0.d, z0.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.experimental.vector.reverse.nxv2i64(<vscale x 2 x i64> %a)
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 8 x half> @reverse_nxv8f16(<vscale x 8 x half> %a) #0 {
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; CHECK-LABEL: reverse_nxv8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev z0.h, z0.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.experimental.vector.reverse.nxv8f16(<vscale x 8 x half> %a)
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ret <vscale x 8 x half> %res
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}
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define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) #0 {
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; CHECK-LABEL: reverse_nxv4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev z0.s, z0.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float> %a) ret <vscale x 4 x float> %res
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}
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define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) #0 {
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; CHECK-LABEL: reverse_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev z0.d, z0.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x double> @llvm.experimental.vector.reverse.nxv2f64(<vscale x 2 x double> %a)
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ret <vscale x 2 x double> %res
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}
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; Verify promote type legalisation works as expected.
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define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) #0 {
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; CHECK-LABEL: reverse_nxv2i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev z0.d, z0.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i8> @llvm.experimental.vector.reverse.nxv2i8(<vscale x 2 x i8> %a)
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ret <vscale x 2 x i8> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <vscale x 8 x i32> @reverse_nxv8i32(<vscale x 8 x i32> %a) #0 {
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; CHECK-LABEL: reverse_nxv8i32:
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; CHECK-SELDAG: // %bb.0:
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; CHECK-SELDAG-NEXT: rev z2.s, z1.s
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; CHECK-SELDAG-NEXT: rev z1.s, z0.s
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; CHECK-SELDAG-NEXT: mov z0.d, z2.d
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; CHECK-SELDAG-NEXT: ret
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; CHECK-FASTISEL: // %bb.0:
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; CHECK-FASTISEL-NEXT: str x29, [sp, #-16]
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; CHECK-FASTISEL-NEXT: addvl sp, sp, #-1
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; CHECK-FASTISEL-NEXT: str z1, [sp]
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; CHECK-FASTISEL-NEXT: mov z1.d, z0.d
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; CHECK-FASTISEL-NEXT: ldr z0, [sp]
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; CHECK-FASTISEL-NEXT: rev z0.s, z0.s
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; CHECK-FASTISEL-NEXT: rev z1.s, z1.s
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; CHECK-FASTISEL-NEXT: addvl sp, sp, #1
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; CHECK-FASTISEL-NEXT: ldr x29, [sp], #16
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; CHECK-FASTISEL-NEXT: ret
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%res = call <vscale x 8 x i32> @llvm.experimental.vector.reverse.nxv8i32(<vscale x 8 x i32> %a)
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ret <vscale x 8 x i32> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) #0 {
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; CHECK-LABEL: reverse_nxv16f32:
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; CHECK-SELDAG: // %bb.0:
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; CHECK-SELDAG-NEXT: rev z5.s, z3.s
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; CHECK-SELDAG-NEXT: rev z4.s, z2.s
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; CHECK-SELDAG-NEXT: rev z2.s, z1.s
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; CHECK-SELDAG-NEXT: rev z3.s, z0.s
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; CHECK-SELDAG-NEXT: mov z0.d, z5.d
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; CHECK-SELDAG-NEXT: mov z1.d, z4.d
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; CHECK-SELDAG-NEXT: ret
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; CHECK-FASTISEL: // %bb.0:
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; CHECK-FASTISEL-NEXT: str x29, [sp, #-16]
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; CHECK-FASTISEL-NEXT: addvl sp, sp, #-2
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; CHECK-FASTISEL-NEXT: str z3, [sp, #1, mul vl]
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; CHECK-FASTISEL-NEXT: str z2, [sp]
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; CHECK-FASTISEL-NEXT: mov z2.d, z1.d
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; CHECK-FASTISEL-NEXT: ldr z1, [sp]
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; CHECK-FASTISEL-NEXT: mov z3.d, z0.d
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; CHECK-FASTISEL-NEXT: ldr z0, [sp, #1, mul vl]
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; CHECK-FASTISEL-NEXT: rev z0.s, z0.s
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; CHECK-FASTISEL-NEXT: rev z1.s, z1.s
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; CHECK-FASTISEL-NEXT: rev z2.s, z2.s
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; CHECK-FASTISEL-NEXT: rev z3.s, z3.s
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; CHECK-FASTISEL-NEXT: addvl sp, sp, #2
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; CHECK-FASTISEL-NEXT: ldr x29, [sp], #16
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; CHECK-FASTISEL-NEXT: ret
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%res = call <vscale x 16 x float> @llvm.experimental.vector.reverse.nxv16f32(<vscale x 16 x float> %a)
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ret <vscale x 16 x float> %res
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}
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declare <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1>)
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declare <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1>)
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declare <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1>)
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declare <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1>)
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declare <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1>)
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declare <vscale x 2 x i8> @llvm.experimental.vector.reverse.nxv2i8(<vscale x 2 x i8>)
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declare <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32>)
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declare <vscale x 8 x i32> @llvm.experimental.vector.reverse.nxv8i32(<vscale x 8 x i32>)
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declare <vscale x 2 x i64> @llvm.experimental.vector.reverse.nxv2i64(<vscale x 2 x i64>)
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declare <vscale x 8 x half> @llvm.experimental.vector.reverse.nxv8f16(<vscale x 8 x half>)
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declare <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float>)
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declare <vscale x 16 x float> @llvm.experimental.vector.reverse.nxv16f32(<vscale x 16 x float>)
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declare <vscale x 2 x double> @llvm.experimental.vector.reverse.nxv2f64(<vscale x 2 x double>)
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attributes #0 = { nounwind "target-features"="+sve" }
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