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6682076a17
This patch introduces a new intrinsic @llvm.experimental.vector.splice that constructs a vector of the same type as the two input vectors, based on a immediate where the sign of the immediate distinguishes two variants. A positive immediate specifies an index into the first vector and a negative immediate specifies the number of trailing elements to extract from the first vector. For example: @llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 1) ==> <B, C, D, E> ; index @llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, -3) ==> <B, C, D, E> ; trailing element count These intrinsics support both fixed and scalable vectors, where the former is lowered to a shufflevector to maintain existing behaviour, although while marked as experimental the recommended way to express this operation for fixed-width vectors is to use shufflevector. For scalable vectors where it is not possible to express a shufflevector mask for this operation, a new ISD node has been implemented. This is one of the named shufflevector intrinsics proposed on the mailing-list in the RFC at [1]. Patch by Paul Walker and Cullen Rhodes. [1] https://lists.llvm.org/pipermail/llvm-dev/2020-November/146864.html Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D94708
143 lines
5.3 KiB
LLVM
143 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; VECTOR_SPLICE (index)
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;
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define <16 x i8> @splice_v16i8_idx(<16 x i8> %a, <16 x i8> %b) #0 {
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; CHECK-LABEL: splice_v16i8_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #1
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; CHECK-NEXT: ret
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%res = call <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1)
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ret <16 x i8> %res
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}
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define <2 x double> @splice_v2f64_idx(<2 x double> %a, <2 x double> %b) #0 {
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; CHECK-LABEL: splice_v2f64_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8
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; CHECK-NEXT: ret
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%res = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 1)
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ret <2 x double> %res
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}
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; Verify promote type legalisation works as expected.
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define <2 x i8> @splice_v2i8_idx(<2 x i8> %a, <2 x i8> %b) #0 {
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; CHECK-LABEL: splice_v2i8_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4
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; CHECK-NEXT: ret
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%res = call <2 x i8> @llvm.experimental.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 1)
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ret <2 x i8> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <8 x i32> @splice_v8i32_idx(<8 x i32> %a, <8 x i32> %b) #0 {
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; CHECK-LABEL: splice_v8i32_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4
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; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4
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; CHECK-NEXT: ret
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%res = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 5)
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ret <8 x i32> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <16 x float> @splice_v16f32_idx(<16 x float> %a, <16 x float> %b) #0 {
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; CHECK-LABEL: splice_v16f32_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12
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; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #12
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; CHECK-NEXT: ext v2.16b, v3.16b, v4.16b, #12
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; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12
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; CHECK-NEXT: ret
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%res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 7)
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ret <16 x float> %res
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}
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; Verify out-of-bounds index results in undef vector.
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define <2 x double> @splice_v2f64_idx_out_of_bounds(<2 x double> %a, <2 x double> %b) #0 {
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; CHECK-LABEL: splice_v2f64_idx_out_of_bounds:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%res = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 2)
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ret <2 x double> %res
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}
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;
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; VECTOR_SPLICE (trailing elements)
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;
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define <16 x i8> @splice_v16i8(<16 x i8> %a, <16 x i8> %b) #0 {
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; CHECK-LABEL: splice_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #1
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; CHECK-NEXT: ret
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%res = call <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 -15)
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ret <16 x i8> %res
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}
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define <2 x double> @splice_v2f64(<2 x double> %a, <2 x double> %b) #0 {
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; CHECK-LABEL: splice_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8
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; CHECK-NEXT: ret
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%res = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 -1)
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ret <2 x double> %res
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}
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; Verify promote type legalisation works as expected.
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define <2 x i8> @splice_v2i8(<2 x i8> %a, <2 x i8> %b) #0 {
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; CHECK-LABEL: splice_v2i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4
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; CHECK-NEXT: ret
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%res = call <2 x i8> @llvm.experimental.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 -1)
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ret <2 x i8> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <8 x i32> @splice_v8i32(<8 x i32> %a, <8 x i32> %b) #0 {
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; CHECK-LABEL: splice_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4
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; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4
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; CHECK-NEXT: ret
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%res = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 -3)
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ret <8 x i32> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <16 x float> @splice_v16f32(<16 x float> %a, <16 x float> %b) #0 {
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; CHECK-LABEL: splice_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12
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; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #12
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; CHECK-NEXT: ext v2.16b, v3.16b, v4.16b, #12
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; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12
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; CHECK-NEXT: ret
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%res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 -9)
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ret <16 x float> %res
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}
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; Verify out-of-bounds trailing element count results in undef vector.
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define <2 x double> @splice_v2f64_out_of_bounds(<2 x double> %a, <2 x double> %b) #0 {
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; CHECK-LABEL: splice_v2f64_out_of_bounds:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%res = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 -3)
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ret <2 x double> %res
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}
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declare <2 x i8> @llvm.experimental.vector.splice.v2i8(<2 x i8>, <2 x i8>, i32)
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declare <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8>, <16 x i8>, i32)
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declare <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32>, <8 x i32>, i32)
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declare <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float>, <16 x float>, i32)
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declare <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double>, <2 x double>, i32)
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attributes #0 = { nounwind "target-features"="+neon" }
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