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c9256d3620
X86 and AArch64 expand it as libcall inside the target. And PowerPC also want to expand them as libcall for P8. So, propose an implement in the legalizer to common the logic and remove the code for X86/AArch64 to avoid the duplicate code. Reviewed By: Craig Topper Differential Revision: https://reviews.llvm.org/D91331
89 lines
3.1 KiB
LLVM
89 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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; Same as vecreduce-fmul-legalization.ll, but without fmf.
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declare half @llvm.vector.reduce.fmul.f16.v1f16(half, <1 x half>)
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declare float @llvm.vector.reduce.fmul.f32.v1f32(float, <1 x float>)
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declare double @llvm.vector.reduce.fmul.f64.v1f64(double, <1 x double>)
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declare fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128, <1 x fp128>)
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declare float @llvm.vector.reduce.fmul.f32.v3f32(float, <3 x float>)
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declare fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128, <2 x fp128>)
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declare float @llvm.vector.reduce.fmul.f32.v16f32(float, <16 x float>)
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define half @test_v1f16(<1 x half> %a) nounwind {
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; CHECK-LABEL: test_v1f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call half @llvm.vector.reduce.fmul.f16.v1f16(half 1.0, <1 x half> %a)
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ret half %b
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}
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define float @test_v1f32(<1 x float> %a) nounwind {
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; CHECK-LABEL: test_v1f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fmul.f32.v1f32(float 1.0, <1 x float> %a)
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ret float %b
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}
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define double @test_v1f64(<1 x double> %a) nounwind {
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; CHECK-LABEL: test_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call double @llvm.vector.reduce.fmul.f64.v1f64(double 1.0, <1 x double> %a)
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ret double %b
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}
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define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v1f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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%b = call fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128 0xL00000000000000003fff00000000000000, <1 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v3f32(<3 x float> %a) nounwind {
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; CHECK-LABEL: test_v3f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmul s1, s0, v0.s[1]
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; CHECK-NEXT: fmul s0, s1, v0.s[2]
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fmul.f32.v3f32(float 1.0, <3 x float> %a)
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ret float %b
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}
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define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
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; CHECK-LABEL: test_v2f128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: b __multf3
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%b = call fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128 0xL00000000000000003fff00000000000000, <2 x fp128> %a)
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ret fp128 %b
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}
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define float @test_v16f32(<16 x float> %a) nounwind {
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; CHECK-LABEL: test_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmul s4, s0, v0.s[1]
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; CHECK-NEXT: fmul s4, s4, v0.s[2]
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; CHECK-NEXT: fmul s0, s4, v0.s[3]
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; CHECK-NEXT: fmul s0, s0, v1.s[0]
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; CHECK-NEXT: fmul s0, s0, v1.s[1]
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; CHECK-NEXT: fmul s0, s0, v1.s[2]
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; CHECK-NEXT: fmul s0, s0, v1.s[3]
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; CHECK-NEXT: fmul s0, s0, v2.s[0]
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; CHECK-NEXT: fmul s0, s0, v2.s[1]
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; CHECK-NEXT: fmul s0, s0, v2.s[2]
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; CHECK-NEXT: fmul s0, s0, v2.s[3]
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; CHECK-NEXT: fmul s0, s0, v3.s[0]
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; CHECK-NEXT: fmul s0, s0, v3.s[1]
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; CHECK-NEXT: fmul s0, s0, v3.s[2]
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; CHECK-NEXT: fmul s0, s0, v3.s[3]
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; CHECK-NEXT: ret
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%b = call float @llvm.vector.reduce.fmul.f32.v16f32(float 1.0, <16 x float> %a)
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ret float %b
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}
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