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c8c6d59c71
This adds lowering for f32 values using the vmov.f16, which zeroes the top bits whilst setting the lower bits to a pattern. This range of values does not often come up, except where a f16 constant value has been converted to a f32. Differential Revision: https://reviews.llvm.org/D87790
192 lines
6.6 KiB
LLVM
192 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple thumbv8m.main-arm-unknown-eabi --float-abi=soft -mattr=+vfp4d16sp < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-VFPV4-SOFT
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; RUN: llc -mtriple thumbv8.1m.main-arm-unknown-eabi --float-abi=soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP16-SOFT
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; RUN: llc -mtriple thumbv8m.main-arm-unknown-eabi --float-abi=hard -mattr=+vfp4d16sp < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-VFPV4-HARD
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; RUN: llc -mtriple thumbv8.1m.main-arm-unknown-eabi --float-abi=hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP16-HARD
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target triple = "thumbv8.1m.main-arm-unknown-eabi"
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define float @add(float %a, float %b) {
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; CHECK-VFPV4-SOFT-LABEL: add:
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; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
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; CHECK-VFPV4-SOFT-NEXT: vmov s0, r1
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; CHECK-VFPV4-SOFT-NEXT: vmov s2, r0
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; CHECK-VFPV4-SOFT-NEXT: vadd.f32 s0, s2, s0
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; CHECK-VFPV4-SOFT-NEXT: vmov r0, s0
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; CHECK-VFPV4-SOFT-NEXT: bx lr
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;
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; CHECK-FP16-SOFT-LABEL: add:
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; CHECK-FP16-SOFT: @ %bb.0: @ %entry
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; CHECK-FP16-SOFT-NEXT: vmov s0, r1
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; CHECK-FP16-SOFT-NEXT: vmov s2, r0
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; CHECK-FP16-SOFT-NEXT: vadd.f32 s0, s2, s0
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; CHECK-FP16-SOFT-NEXT: vmov r0, s0
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; CHECK-FP16-SOFT-NEXT: bx lr
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;
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; CHECK-VFPV4-HARD-LABEL: add:
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; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
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; CHECK-VFPV4-HARD-NEXT: vadd.f32 s0, s0, s1
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; CHECK-VFPV4-HARD-NEXT: bx lr
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;
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; CHECK-FP16-HARD-LABEL: add:
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; CHECK-FP16-HARD: @ %bb.0: @ %entry
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; CHECK-FP16-HARD-NEXT: vadd.f32 s0, s0, s1
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; CHECK-FP16-HARD-NEXT: bx lr
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entry:
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%add = fadd float %a, %b
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ret float %add
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}
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define half @addf16(half %a, half %b) {
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; CHECK-VFPV4-SOFT-LABEL: addf16:
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; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
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; CHECK-VFPV4-SOFT-NEXT: vmov s0, r0
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; CHECK-VFPV4-SOFT-NEXT: vmov s2, r1
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; CHECK-VFPV4-SOFT-NEXT: vcvtb.f32.f16 s0, s0
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; CHECK-VFPV4-SOFT-NEXT: vcvtb.f32.f16 s2, s2
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; CHECK-VFPV4-SOFT-NEXT: vadd.f32 s0, s0, s2
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; CHECK-VFPV4-SOFT-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-VFPV4-SOFT-NEXT: vmov r0, s0
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; CHECK-VFPV4-SOFT-NEXT: bx lr
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;
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; CHECK-FP16-SOFT-LABEL: addf16:
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; CHECK-FP16-SOFT: @ %bb.0: @ %entry
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; CHECK-FP16-SOFT-NEXT: vmov.f16 s0, r1
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; CHECK-FP16-SOFT-NEXT: vmov.f16 s2, r0
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; CHECK-FP16-SOFT-NEXT: vadd.f16 s0, s2, s0
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; CHECK-FP16-SOFT-NEXT: vmov r0, s0
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; CHECK-FP16-SOFT-NEXT: bx lr
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;
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; CHECK-VFPV4-HARD-LABEL: addf16:
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; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
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; CHECK-VFPV4-HARD-NEXT: vcvtb.f32.f16 s2, s1
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; CHECK-VFPV4-HARD-NEXT: vcvtb.f32.f16 s0, s0
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; CHECK-VFPV4-HARD-NEXT: vadd.f32 s0, s0, s2
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; CHECK-VFPV4-HARD-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-VFPV4-HARD-NEXT: bx lr
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;
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; CHECK-FP16-HARD-LABEL: addf16:
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; CHECK-FP16-HARD: @ %bb.0: @ %entry
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; CHECK-FP16-HARD-NEXT: vadd.f16 s0, s0, s1
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; CHECK-FP16-HARD-NEXT: bx lr
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entry:
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%add = fadd half %a, %b
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ret half %add
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}
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define half @load_i16(i16 *%hp) {
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; CHECK-VFPV4-SOFT-LABEL: load_i16:
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; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
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; CHECK-VFPV4-SOFT-NEXT: vmov.f32 s0, #1.000000e+00
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; CHECK-VFPV4-SOFT-NEXT: ldrh r0, [r0]
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; CHECK-VFPV4-SOFT-NEXT: vmov s2, r0
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; CHECK-VFPV4-SOFT-NEXT: vcvtb.f32.f16 s2, s2
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; CHECK-VFPV4-SOFT-NEXT: vadd.f32 s0, s2, s0
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; CHECK-VFPV4-SOFT-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-VFPV4-SOFT-NEXT: vmov r0, s0
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; CHECK-VFPV4-SOFT-NEXT: bx lr
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;
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; CHECK-FP16-SOFT-LABEL: load_i16:
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; CHECK-FP16-SOFT: @ %bb.0: @ %entry
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; CHECK-FP16-SOFT-NEXT: vldr.16 s2, [r0]
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; CHECK-FP16-SOFT-NEXT: vmov.f16 s0, #1.000000e+00
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; CHECK-FP16-SOFT-NEXT: vadd.f16 s0, s2, s0
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; CHECK-FP16-SOFT-NEXT: vmov r0, s0
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; CHECK-FP16-SOFT-NEXT: bx lr
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;
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; CHECK-VFPV4-HARD-LABEL: load_i16:
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; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
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; CHECK-VFPV4-HARD-NEXT: vmov.f32 s0, #1.000000e+00
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; CHECK-VFPV4-HARD-NEXT: ldrh r0, [r0]
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; CHECK-VFPV4-HARD-NEXT: vmov s2, r0
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; CHECK-VFPV4-HARD-NEXT: vcvtb.f32.f16 s2, s2
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; CHECK-VFPV4-HARD-NEXT: vadd.f32 s0, s2, s0
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; CHECK-VFPV4-HARD-NEXT: vcvtb.f16.f32 s0, s0
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; CHECK-VFPV4-HARD-NEXT: bx lr
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;
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; CHECK-FP16-HARD-LABEL: load_i16:
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; CHECK-FP16-HARD: @ %bb.0: @ %entry
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; CHECK-FP16-HARD-NEXT: vldr.16 s2, [r0]
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; CHECK-FP16-HARD-NEXT: vmov.f16 s0, #1.000000e+00
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; CHECK-FP16-HARD-NEXT: vadd.f16 s0, s2, s0
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; CHECK-FP16-HARD-NEXT: bx lr
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entry:
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%h = load i16, i16 *%hp, align 2
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%hc = bitcast i16 %h to half
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%add = fadd half %hc, 1.0
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ret half %add
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}
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define i16 @load_f16(half *%hp) {
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; CHECK-LABEL: load_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ldrh r0, [r0]
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; CHECK-NEXT: adds r0, #1
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; CHECK-NEXT: bx lr
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entry:
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%h = load half, half *%hp, align 2
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%hc = bitcast half %h to i16
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%add = add i16 %hc, 1
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ret i16 %add
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}
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define half @constcall() {
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; CHECK-VFPV4-SOFT-LABEL: constcall:
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; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
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; CHECK-VFPV4-SOFT-NEXT: mov.w r0, #18688
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; CHECK-VFPV4-SOFT-NEXT: b ccc
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;
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; CHECK-FP16-SOFT-LABEL: constcall:
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; CHECK-FP16-SOFT: @ %bb.0: @ %entry
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; CHECK-FP16-SOFT-NEXT: mov.w r0, #18688
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; CHECK-FP16-SOFT-NEXT: b ccc
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;
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; CHECK-VFPV4-HARD-LABEL: constcall:
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; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
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; CHECK-VFPV4-HARD-NEXT: vldr s0, .LCPI4_0
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; CHECK-VFPV4-HARD-NEXT: b ccc
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; CHECK-VFPV4-HARD-NEXT: .p2align 2
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; CHECK-VFPV4-HARD-NEXT: @ %bb.1:
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; CHECK-VFPV4-HARD-NEXT: .LCPI4_0:
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; CHECK-VFPV4-HARD-NEXT: .long 0x00004900 @ float 2.61874657E-41
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;
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; CHECK-FP16-HARD-LABEL: constcall:
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; CHECK-FP16-HARD: @ %bb.0: @ %entry
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; CHECK-FP16-HARD-NEXT: vmov.f16 s0, #1.000000e+01
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; CHECK-FP16-HARD-NEXT: b ccc
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entry:
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%call = tail call fast half @ccc(half 0xH4900)
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ret half %call
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}
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define half @constret() {
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; CHECK-VFPV4-SOFT-LABEL: constret:
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; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
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; CHECK-VFPV4-SOFT-NEXT: mov.w r0, #18688
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; CHECK-VFPV4-SOFT-NEXT: bx lr
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;
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; CHECK-FP16-SOFT-LABEL: constret:
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; CHECK-FP16-SOFT: @ %bb.0: @ %entry
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; CHECK-FP16-SOFT-NEXT: vmov.f16 s0, #1.000000e+01
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; CHECK-FP16-SOFT-NEXT: vmov r0, s0
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; CHECK-FP16-SOFT-NEXT: bx lr
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;
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; CHECK-VFPV4-HARD-LABEL: constret:
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; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
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; CHECK-VFPV4-HARD-NEXT: vldr s0, .LCPI5_0
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; CHECK-VFPV4-HARD-NEXT: bx lr
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; CHECK-VFPV4-HARD-NEXT: .p2align 2
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; CHECK-VFPV4-HARD-NEXT: @ %bb.1:
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; CHECK-VFPV4-HARD-NEXT: .LCPI5_0:
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; CHECK-VFPV4-HARD-NEXT: .long 0x00004900 @ float 2.61874657E-41
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;
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; CHECK-FP16-HARD-LABEL: constret:
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; CHECK-FP16-HARD: @ %bb.0: @ %entry
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; CHECK-FP16-HARD-NEXT: vmov.f16 s0, #1.000000e+01
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; CHECK-FP16-HARD-NEXT: bx lr
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entry:
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ret half 0xH4900
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}
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declare half @ccc(half)
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