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bbf5be9d55
This adds infrastructure to print and parse MIR MachineOperand comments. The motivation for the ARM backend is to print condition code names instead of magic constants that are difficult to read (for human beings). For example, instead of this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg t2Bcc %bb.4, 0, killed $cpsr we now print this: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 /* CC::always */, $noreg t2Bcc %bb.4, 0 /* CC:eq */, killed $cpsr This shows that MachineOperand comments are enclosed between /* and */. In this example, the EOR instruction is not conditionally executed (i.e. it is "always executed"), which is encoded by the 14 immediate machine operand. Thus, now this machine operand has /* CC::always */ as a comment. The 0 on the next conditional branch instruction represents the equal condition code, thus now this operand has /* CC:eq */ as a comment. As it is a comment, the MI lexer/parser completely ignores it. The benefit is that this keeps the change in the lexer extremely minimal and no target specific parsing needs to be done. The changes on the MIPrinter side are also minimal, as there is only one target hooks that is used to create the machine operand comments. Differential Revision: https://reviews.llvm.org/D74306
82 lines
3.5 KiB
YAML
82 lines
3.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -start-before simple-register-coalescing -mtriple=arm-apple-ios -stop-after machine-scheduler -o - -arm-enable-subreg-liveness -verify-machineinstrs | FileCheck %s
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# Check that when we merge live-ranges that imply offseting
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# the definition of a subregister by some other subreg index,
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# we take that new index into account while updating the subrange.
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#
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# For this specific test case, the coalescer is going to get rid
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# of `%5.dsub_1:dtriple = COPY %4.dsub_3` by aligning
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# %5.dsub_1:<3 x s64> with %4.dsub_3:<4 x s64>.
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# This is done by moving to a bigger register class <5 x s64>
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# and offseting %5 definitions with a new subregidx:
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# NewVar: <5 x s64> dsub_0 dsub_1 dsub_2 dsub_3 dsub_4
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# %4: <4 x s64> dsub_0 dsub_1 dsub_2 dsub_3
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# %5: <3 x s64> <==offset===> dsub_0 dsub_1 dsub_2
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#
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# In other %5.dsub_0 needs to be mapped to NewVar.dsub_2, %5.dsub_1
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# to NewVar.dsub_3 and so on. So essentially we are offseting %5 by
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# dsub_2.
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#
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# When updating the live-ranges, the register coalescer actually
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# has not rewritten the original code, so we need to fake the
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# rewrite to do that update.
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# This used to be wrong and this test was failling with a machine
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# verifier error: No live segment at def.
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#
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# The test case runs through the coalescer *and* the scheduler, just
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# to force the live intervals to be carried around so that the verifier
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# gets a chance to verify those. If we were to just run the coalescer,
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# the live intervals would be dropped before running the verifier since
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# no other pass would need that analysis around.
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#
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# Note: The test case looks slightly more complicated than just the
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# offseting part. That's because the bug needs three things to
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# trigger:
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# 1. Overlapping subreg lanes: here, dsub0 == <ssub0, ssub1>
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# 2. Tuple registers with a possibility to coalesce the subreg index:
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# here, what we explain with %5.dsub_1 == %4.dsub_3
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# 3. Subreg liveness enabled.
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# #1 is required to trigger the splitting of subranges that implies
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# looking at the IR to decide what is alive and what is not.
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# #2 is what produces the IR to be out-of-synce with what the reg coalescer
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# maintains for the live-ranges information.
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# #3 is, well, the problem has to do with subranges updates!
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#
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# In the end, the expected result is to have all the variables
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# being coalesced in one big (qqqq) variable.
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---
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name: main
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alignment: 1
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d2, $s1, $d4
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; CHECK-LABEL: name: main
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; CHECK: liveins: $d2, $s1, $d4
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; CHECK: undef %4.dsub_0:qqqqpr_with_ssub_4 = COPY $d4
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; CHECK: %4.ssub_4:qqqqpr_with_ssub_4 = COPY $s1
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; CHECK: %4.dsub_1:qqqqpr_with_ssub_4 = COPY $d2
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; CHECK: %4.dsub_3:qqqqpr_with_ssub_4 = COPY %4.dsub_1
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; CHECK: KILL implicit-def %4.dsub_2, implicit %4.qqsub_0
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; CHECK: %4.dsub_4:qqqqpr_with_ssub_4 = COPY %4.dsub_1
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %4.ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9
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%3:dpr_vfp2 = COPY $d4
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undef %0.ssub_0:dpr_vfp2 = COPY $s1
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%1:dpr_vfp2 = COPY $d2
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undef %4.dsub_0:dquad = COPY %3
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%4.dsub_1:dquad = COPY %1
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%4.dsub_2:dquad = COPY %0
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%4.dsub_3:dquad = COPY %1
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KILL implicit-def undef %5.dsub_0:dtriple, implicit %4
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%5.dsub_1:dtriple = COPY %4.dsub_3
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%5.dsub_2:dtriple = COPY %1
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tBX_RET 14, $noreg, implicit %5
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...
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