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cc12b285b6
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
383 lines
10 KiB
YAML
383 lines
10 KiB
YAML
# RUN: llc -run-pass=arm-cp-islands -o - %s | FileCheck %s
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# Test created by tweaking the register allocation after stopping the IR below
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# just before constant islands. We were forwarding the table index to the end of
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# the block, even though the LEA clobbered it.
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# CHECK-LABEL: name: foo
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# CHECK: tBR_JT
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# This order is important. If the jump-table comes first then the
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# transformation is valid because the LEA can be removed, see second test.
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# CHECK: CONSTPOOL_ENTRY
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# CHECK: JUMPTABLE_ADDRS
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# CHECK-LABEL: name: bar
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# CHECK: tTBB_JT $pc, killed $r1
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--- |
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; ModuleID = 'simple.ll'
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source_filename = "simple.ll"
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv6m-none--eabi"
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define void @foo(i8 %in, i32* %addr) {
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store i32 12345678, i32* %addr
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%1 = call i32 @llvm.arm.space(i32 980, i32 undef)
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%2 = zext i8 %in to i32
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switch i32 %2, label %default [
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i32 0, label %d1
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i32 1, label %d2
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i32 3, label %d3
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i32 4, label %d4
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i32 5, label %d5
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i32 6, label %d6
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i32 7, label %d7
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i32 2, label %d8
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i32 8, label %d9
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i32 9, label %d10
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i32 19, label %d11
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i32 20, label %d12
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i32 21, label %d13
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i32 22, label %d14
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i32 24, label %d15
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i32 25, label %d16
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i32 26, label %d17
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]
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default: ; preds = %0
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unreachable
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d1: ; preds = %0
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unreachable
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d2: ; preds = %0
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unreachable
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d3: ; preds = %0
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unreachable
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d4: ; preds = %0
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unreachable
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d5: ; preds = %0
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unreachable
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d6: ; preds = %0
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unreachable
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d7: ; preds = %0
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unreachable
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d8: ; preds = %0
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unreachable
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d9: ; preds = %0
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unreachable
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d10: ; preds = %0
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unreachable
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d11: ; preds = %0
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unreachable
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d12: ; preds = %0
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unreachable
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d13: ; preds = %0
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unreachable
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d14: ; preds = %0
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unreachable
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d15: ; preds = %0
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unreachable
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d16: ; preds = %0
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unreachable
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d17: ; preds = %0
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unreachable
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}
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define void @bar(i8 %in, i32* %addr) {
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store i32 12345678, i32* %addr
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%1 = zext i8 %in to i32
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switch i32 %1, label %default [
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i32 0, label %d1
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i32 1, label %d2
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i32 3, label %d3
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i32 4, label %d4
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i32 5, label %d5
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i32 6, label %d6
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i32 7, label %d7
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i32 2, label %d8
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i32 8, label %d9
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i32 9, label %d10
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i32 19, label %d11
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i32 20, label %d12
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i32 21, label %d13
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i32 22, label %d14
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i32 24, label %d15
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i32 25, label %d16
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i32 26, label %d17
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]
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default: ; preds = %0
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unreachable
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d1: ; preds = %0
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unreachable
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d2: ; preds = %0
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unreachable
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d3: ; preds = %0
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unreachable
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d4: ; preds = %0
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unreachable
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d5: ; preds = %0
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unreachable
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d6: ; preds = %0
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unreachable
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d7: ; preds = %0
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unreachable
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d8: ; preds = %0
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unreachable
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d9: ; preds = %0
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unreachable
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d10: ; preds = %0
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unreachable
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d11: ; preds = %0
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unreachable
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d12: ; preds = %0
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unreachable
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d13: ; preds = %0
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unreachable
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d14: ; preds = %0
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unreachable
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d15: ; preds = %0
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unreachable
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d16: ; preds = %0
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unreachable
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d17: ; preds = %0
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unreachable
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}
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; Function Attrs: nounwind
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declare i32 @llvm.arm.space(i32, i32) #0
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #0
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attributes #0 = { nounwind }
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...
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---
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name: foo
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0' }
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- { reg: '$r1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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constants:
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- id: 0
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value: i32 12345678
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alignment: 4
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jumpTable:
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kind: inline
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entries:
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- id: 0
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blocks: [ '%bb.3.d2', '%bb.9.d8', '%bb.4.d3', '%bb.5.d4',
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'%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9',
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'%bb.11.d10', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
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'%bb.2.d1', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
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'%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12',
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'%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15',
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'%bb.17.d16', '%bb.18.d17' ]
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body: |
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bb.0 (%ir-block.0):
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successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
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liveins: $r0, $r1
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$r2 = tLDRpci %const.0, 14, $noreg
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tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store (s32) into %ir.addr)
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dead $r1 = SPACE 980, undef $r0
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$r0 = tUXTB killed $r0, 14, $noreg
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$r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg
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tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2.d1, 8, killed $cpsr
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bb.1 (%ir-block.0):
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successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
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liveins: $r1
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$r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
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$r1 = tLEApcrelJT %jump-table.0, 14, $noreg
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$r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load (s32) from jump-table)
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tBR_JTr killed $r0, %jump-table.0
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bb.3.d2:
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bb.9.d8:
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bb.4.d3:
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bb.5.d4:
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bb.6.d5:
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bb.7.d6:
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bb.8.d7:
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bb.10.d9:
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bb.11.d10:
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bb.2.d1:
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bb.12.d11:
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bb.13.d12:
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bb.14.d13:
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bb.15.d14:
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bb.16.d15:
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bb.17.d16:
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bb.18.d17:
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...
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---
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name: bar
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '$r0' }
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- { reg: '$r1' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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constants:
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- id: 0
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value: i32 12345678
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alignment: 4
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jumpTable:
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kind: inline
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entries:
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- id: 0
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blocks: [ '%bb.3.d2', '%bb.9.d8', '%bb.4.d3', '%bb.5.d4',
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'%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9',
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'%bb.11.d10', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
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'%bb.2.d1', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
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'%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12',
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'%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15',
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'%bb.17.d16', '%bb.18.d17' ]
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body: |
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bb.0 (%ir-block.0):
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successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
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liveins: $r0, $r1
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$r2 = tLDRpci %const.0, 14, $noreg
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tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store (s32) into %ir.addr)
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$r0 = tUXTB killed $r0, 14, $noreg
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$r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg
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tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2.d1, 8, killed $cpsr
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bb.1 (%ir-block.0):
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successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
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liveins: $r1
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$r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
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$r1 = tLEApcrelJT %jump-table.0, 14, $noreg
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$r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load (s32) from jump-table)
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tBR_JTr killed $r0, %jump-table.0
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bb.3.d2:
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bb.9.d8:
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bb.4.d3:
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bb.5.d4:
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bb.6.d5:
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bb.7.d6:
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bb.8.d7:
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bb.10.d9:
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bb.11.d10:
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bb.2.d1:
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bb.12.d11:
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bb.13.d12:
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bb.14.d13:
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bb.15.d14:
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bb.16.d15:
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bb.17.d16:
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bb.18.d17:
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...
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