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ee0d5cd952
This adds support for the new 32-bit vector float instructions of z14. This includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions, including new LLVM intrinsics. - Scheduler description support for the instructions. - Update to the vector cost function calculations. In general, CodeGen support for the new v4f32 instructions closely matches support for the existing v2f64 instructions. llvm-svn: 308195
24 lines
609 B
LLVM
24 lines
609 B
LLVM
; Test f32 and v4f32 square root on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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declare float @llvm.sqrt.f32(float)
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declare <4 x float> @llvm.sqrt.v4f32(<4 x float>)
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define <4 x float> @f1(<4 x float> %val) {
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; CHECK-LABEL: f1:
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; CHECK: vfsqsb %v24, %v24
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; CHECK: br %r14
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%ret = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %val)
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ret <4 x float> %ret
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}
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define float @f2(<4 x float> %val) {
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; CHECK-LABEL: f2:
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; CHECK: wfsqsb %f0, %v24
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; CHECK: br %r14
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%scalar = extractelement <4 x float> %val, i32 0
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%ret = call float @llvm.sqrt.f32(float %scalar)
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ret float %ret
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}
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