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81bb5f99ad
The data layout strings do not have any effect on llc tests and will become misleadingly out of date as we continue to update the canonical data layout, so remove them from the tests. Differential Revision: https://reviews.llvm.org/D105842
36 lines
1.1 KiB
LLVM
36 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "wasm32-unknown-unknown"
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; Regression test for pr47375, in which an assertion was triggering
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; because WebAssemblyTargetLowering::isVectorLoadExtDesirable was
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; improperly assuming the use of simple value types.
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define void @sext_vec() {
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; CHECK-LABEL: sext_vec:
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; CHECK: .functype sext_vec () -> ()
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; CHECK-NEXT: .local i32
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; CHECK-NEXT: # %bb.0:
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32.load8_u 0
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; CHECK-NEXT: local.set 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32.const 0
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; CHECK-NEXT: i32.store8 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32.const 7
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; CHECK-NEXT: i32.shl
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; CHECK-NEXT: i32.or
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; CHECK-NEXT: i32.const 7175
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; CHECK-NEXT: i32.and
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; CHECK-NEXT: i32.store16 0
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; CHECK-NEXT: # fallthrough-return
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%L1 = load <2 x i3>, <2 x i3>* undef, align 2
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%zext = zext <2 x i3> %L1 to <2 x i10>
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store <2 x i10> %zext, <2 x i10>* undef, align 4
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ret void
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}
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