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e263936592
The freeze issue was reported here https://llvm.discourse.group/t/bug-or-feature-freeze-instruction/3639 I don't have a test for AssertAlign. I just noticed it was missing and assume it should be similar to the other two Asserts. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D104178
148 lines
3.8 KiB
LLVM
148 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s 2>&1 | FileCheck %s --check-prefix=X86ASM
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%struct.T = type { i32, i32 }
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define i32 @freeze_int() {
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; X86ASM-LABEL: freeze_int:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: imull %eax, %eax
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; X86ASM-NEXT: retq
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%y1 = freeze i32 undef
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%t1 = mul i32 %y1, %y1
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ret i32 %t1
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}
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define i5 @freeze_int2() {
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; X86ASM-LABEL: freeze_int2:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: mulb %al
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; X86ASM-NEXT: retq
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%y1 = freeze i5 undef
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%t1 = mul i5 %y1, %y1
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ret i5 %t1
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}
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define float @freeze_float() {
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; X86ASM-LABEL: freeze_float:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: addss %xmm0, %xmm0
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; X86ASM-NEXT: retq
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%y1 = freeze float undef
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%t1 = fadd float %y1, %y1
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ret float %t1
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}
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define half @freeze_half() {
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; X86ASM-LABEL: freeze_half:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: pushq %rax
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; X86ASM-NEXT: .cfi_def_cfa_offset 16
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; X86ASM-NEXT: xorl %edi, %edi
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; X86ASM-NEXT: callq __gnu_h2f_ieee@PLT
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; X86ASM-NEXT: callq __gnu_f2h_ieee@PLT
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; X86ASM-NEXT: movzwl %ax, %edi
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; X86ASM-NEXT: callq __gnu_h2f_ieee@PLT
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; X86ASM-NEXT: addss %xmm0, %xmm0
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; X86ASM-NEXT: callq __gnu_f2h_ieee@PLT
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; X86ASM-NEXT: popq %rcx
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; X86ASM-NEXT: .cfi_def_cfa_offset 8
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; X86ASM-NEXT: retq
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%y1 = freeze half undef
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%t1 = fadd half %y1, %y1
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ret half %t1
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}
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define <2 x i32> @freeze_ivec() {
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; X86ASM-LABEL: freeze_ivec:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: paddd %xmm0, %xmm0
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; X86ASM-NEXT: retq
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%y1 = freeze <2 x i32> undef
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%t1 = add <2 x i32> %y1, %y1
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ret <2 x i32> %t1
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}
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define i8* @freeze_ptr() {
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; X86ASM-LABEL: freeze_ptr:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: addq $4, %rax
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; X86ASM-NEXT: retq
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%y1 = freeze i8* undef
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%t1 = getelementptr i8, i8* %y1, i64 4
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ret i8* %t1
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}
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define i32 @freeze_struct() {
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; X86ASM-LABEL: freeze_struct:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: addl %eax, %eax
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; X86ASM-NEXT: retq
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%y1 = freeze %struct.T undef
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%v1 = extractvalue %struct.T %y1, 0
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%v2 = extractvalue %struct.T %y1, 1
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%t1 = add i32 %v1, %v2
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ret i32 %t1
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}
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define i32 @freeze_anonstruct() {
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; X86ASM-LABEL: freeze_anonstruct:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: addl %eax, %eax
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; X86ASM-NEXT: retq
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%y1 = freeze {i32, i32} undef
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%v1 = extractvalue {i32, i32} %y1, 0
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%v2 = extractvalue {i32, i32} %y1, 1
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%t1 = add i32 %v1, %v2
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ret i32 %t1
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}
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define i32 @freeze_anonstruct2() {
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; X86ASM-LABEL: freeze_anonstruct2:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: movzwl %ax, %eax
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; X86ASM-NEXT: addl %eax, %eax
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; X86ASM-NEXT: retq
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%y1 = freeze {i32, i16} undef
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%v1 = extractvalue {i32, i16} %y1, 0
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%v2 = extractvalue {i32, i16} %y1, 1
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%z2 = zext i16 %v2 to i32
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%t1 = add i32 %v1, %z2
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ret i32 %t1
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}
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define i64 @freeze_array() {
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; X86ASM-LABEL: freeze_array:
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; X86ASM: # %bb.0:
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; X86ASM-NEXT: addq %rax, %rax
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; X86ASM-NEXT: retq
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%y1 = freeze [2 x i64] undef
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%v1 = extractvalue [2 x i64] %y1, 0
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%v2 = extractvalue [2 x i64] %y1, 1
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%t1 = add i64 %v1, %v2
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ret i64 %t1
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}
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; Make sure we emit a movl to zext the input before the imulq. This previously
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; failed because freeze was not listed in the instructions that don't zext their
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; result in the def32 pattern X86InstrCompiler.td.
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define i32 @freeze_zext(i64 %a) nounwind {
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; X86ASM-LABEL: freeze_zext:
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; X86ASM: # %bb.0: # %entry
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; X86ASM-NEXT: movq %rdi, %rax
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; X86ASM-NEXT: movl %eax, %ecx
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; X86ASM-NEXT: movl $3435973837, %edx # imm = 0xCCCCCCCD
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; X86ASM-NEXT: imulq %rcx, %rdx
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; X86ASM-NEXT: shrq $35, %rdx
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; X86ASM-NEXT: addl %edx, %edx
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; X86ASM-NEXT: leal (%rdx,%rdx,4), %ecx
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; X86ASM-NEXT: subl %ecx, %eax
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; X86ASM-NEXT: # kill: def $eax killed $eax killed $rax
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; X86ASM-NEXT: retq
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entry:
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%x = trunc i64 %a to i32
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%y = freeze i32 %x
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%z = urem i32 %y, 10
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ret i32 %z
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}
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