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ccc67b1eb8
lrint/llrint are defined as rounding using the current rounding mode. Numbers that can't be converted raise FE_INVALID and an implementation defined value is returned. They may also write to errno. I believe this means we can use cvtss2si/cvtsd2si or fist to convert as long as -fno-math-errno is passed on the command line. Clang will leave them as libcalls if errno is enabled so they won't become ISD::LRINT/LLRINT in SelectionDAG. For 64-bit results on a 32-bit target we can't use cvtss2si/cvtsd2si but we can use fist since it can write to a 64-bit memory location. Though maybe we could consider using vcvtps2qq/vcvtpd2qq on avx512dq targets? gcc also does this optimization. I think we might be able to do this with STRICT_LRINT/LLRINT as well, but I've left that for future work. Differential Revision: https://reviews.llvm.org/D73859
108 lines
3.5 KiB
LLVM
108 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefixes=X86,X86-NOSSE
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; RUN: llc < %s -mtriple=i686-unknown -mattr=sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
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; RUN: llc < %s -mtriple=i686-unknown -mattr=avx | FileCheck %s --check-prefixes=X86,X86-AVX
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; RUN: llc < %s -mtriple=i686-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X86,X86-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64,X64-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64-AVX
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define i32 @testmsws(float %x) {
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; X86-NOSSE-LABEL: testmsws:
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; X86-NOSSE: # %bb.0: # %entry
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; X86-NOSSE-NEXT: pushl %eax
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; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
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; X86-NOSSE-NEXT: flds {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: fistpl (%esp)
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; X86-NOSSE-NEXT: movl (%esp), %eax
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; X86-NOSSE-NEXT: popl %ecx
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; X86-NOSSE-NEXT: .cfi_def_cfa_offset 4
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; X86-NOSSE-NEXT: retl
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;
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; X86-SSE2-LABEL: testmsws:
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; X86-SSE2: # %bb.0: # %entry
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; X86-SSE2-NEXT: cvtss2si {{[0-9]+}}(%esp), %eax
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; X86-SSE2-NEXT: retl
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;
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; X86-AVX-LABEL: testmsws:
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; X86-AVX: # %bb.0: # %entry
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; X86-AVX-NEXT: vcvtss2si {{[0-9]+}}(%esp), %eax
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; X86-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: testmsws:
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; X64-SSE: # %bb.0: # %entry
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; X64-SSE-NEXT: cvtss2si %xmm0, %eax
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: testmsws:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: vcvtss2si %xmm0, %eax
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; X64-AVX-NEXT: retq
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entry:
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%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
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ret i32 %0
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}
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define i32 @testmswd(double %x) {
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; X86-NOSSE-LABEL: testmswd:
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; X86-NOSSE: # %bb.0: # %entry
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; X86-NOSSE-NEXT: pushl %eax
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; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
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; X86-NOSSE-NEXT: fldl {{[0-9]+}}(%esp)
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; X86-NOSSE-NEXT: fistpl (%esp)
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; X86-NOSSE-NEXT: movl (%esp), %eax
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; X86-NOSSE-NEXT: popl %ecx
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; X86-NOSSE-NEXT: .cfi_def_cfa_offset 4
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; X86-NOSSE-NEXT: retl
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;
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; X86-SSE2-LABEL: testmswd:
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; X86-SSE2: # %bb.0: # %entry
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; X86-SSE2-NEXT: cvtsd2si {{[0-9]+}}(%esp), %eax
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; X86-SSE2-NEXT: retl
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;
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; X86-AVX-LABEL: testmswd:
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; X86-AVX: # %bb.0: # %entry
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; X86-AVX-NEXT: vcvtsd2si {{[0-9]+}}(%esp), %eax
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; X86-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: testmswd:
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; X64-SSE: # %bb.0: # %entry
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; X64-SSE-NEXT: cvtsd2si %xmm0, %eax
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: testmswd:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: vcvtsd2si %xmm0, %eax
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; X64-AVX-NEXT: retq
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entry:
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%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
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ret i32 %0
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}
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define i32 @testmsll(x86_fp80 %x) {
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; X86-LABEL: testmsll:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %eax
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: fldt {{[0-9]+}}(%esp)
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; X86-NEXT: fistpl (%esp)
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; X86-NEXT: movl (%esp), %eax
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; X86-NEXT: popl %ecx
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; X86-NEXT: .cfi_def_cfa_offset 4
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; X86-NEXT: retl
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;
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; X64-LABEL: testmsll:
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; X64: # %bb.0: # %entry
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; X64-NEXT: fldt {{[0-9]+}}(%rsp)
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; X64-NEXT: fistpl -{{[0-9]+}}(%rsp)
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; X64-NEXT: movl -{{[0-9]+}}(%rsp), %eax
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; X64-NEXT: retq
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entry:
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%0 = tail call i32 @llvm.lrint.i32.f80(x86_fp80 %x)
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ret i32 %0
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}
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declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
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declare i32 @llvm.lrint.i32.f64(double) nounwind readnone
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declare i32 @llvm.lrint.i32.f80(x86_fp80) nounwind readnone
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