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f6f886a614
This demonstrates a possible fix for PR48760 - for compares with constants, canonicalize the SGT/UGT condition code to use SGE/UGE which should reduce the number of EFLAGs bits we need to read. As discussed on PR48760, some EFLAG bits are treated independently which can require additional uops to merge together for certain CMOVcc/SETcc/etc. modes. I've limited this to cases where the constant increment doesn't result in a larger encoding or additional i64 constant materializations. Differential Revision: https://reviews.llvm.org/D101074
29 lines
1.3 KiB
LLVM
29 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 --x86-asm-syntax=intel -mtriple=x86_64-grtev4-linux-gnu -march=x86-64 -mcpu=skylake-avx512 -mattr=fma,avx512f < %s | FileCheck %s
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define <4 x i1> @selecter(i64 %0) {
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; CHECK-LABEL: selecter:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xor eax, eax
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; CHECK-NEXT: cmp rdi, 2
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; CHECK-NEXT: setge al
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; CHECK-NEXT: lea eax, [rax + 2*rax]
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; CHECK-NEXT: kmovd k0, eax
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; CHECK-NEXT: vpmovm2d xmm0, k0
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; CHECK-NEXT: ret
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%2 = icmp slt i64 0, %0
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%3 = select i1 %2, <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i1> zeroinitializer
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%4 = insertvalue [4 x <4 x i1>] zeroinitializer, <4 x i1> %3, 0
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%5 = icmp slt i64 1, %0
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%6 = select i1 %5, <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i1> zeroinitializer
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%7 = insertvalue [4 x <4 x i1>] %4, <4 x i1> %6, 1
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%8 = icmp slt i64 2, %0
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%9 = select i1 %8, <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i1> zeroinitializer
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%10 = insertvalue [4 x <4 x i1>] %7, <4 x i1> %9, 2
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%11 = icmp slt i64 3, %0
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%12 = select i1 %11, <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i1> zeroinitializer
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%13 = insertvalue [4 x <4 x i1>] %10, <4 x i1> %12, 3
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%14 = extractvalue [4 x <4 x i1>] %13, 1
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ret <4 x i1> %14
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}
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