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47e9765193
No register can be allocated for indirect call when it use regcall calling convention and passed 5/5+ args. For example: call vreg (ag1, ag2, ag3, ag4, ag5, ...) --> 5 regs (EAX, ECX, EDX, ESI, EDI) used for pass args, 1 reg (EBX )used for hold GOT point, so no regs can be allocated to vreg. The Intel386 architecture provides 8 general purpose 32-bit registers. RA mostly use 6 of them (EAX, EBX, ECX, EDX, ESI, EDI). 5 of this regs can be used to pass function arguments (EAX, ECX, EDX, ESI, EDI). EBX used to hold the GOT pointer when making function calls via the PLT. ESP and EBP usually be "reserved" in register allocation. Reviewed By: LuoYuanke Differential Revision: https://reviews.llvm.org/D91020
27 lines
746 B
LLVM
27 lines
746 B
LLVM
; RUN: llc < %s -mtriple=i386-pc-unknown-linux-gnu -relocation-model=pic | FileCheck %s
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@a0 = global i32 0, align 4
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define x86_regcallcc void @tail_call_regcall(i32 %a) nounwind {
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tail call x86_regcallcc void @__regcall3__func(i32 %a) nounwind
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ret void
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}
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define internal x86_regcallcc void @__regcall3__func(i32 %i1) {
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entry:
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store i32 %i1, i32* @a0, align 4
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ret void
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}
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;CHECK-LABLE: tail_call_regcall:
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;CHECK: # %bb.0:
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;CHECK-NEXT: jmp __regcall3__func # TAILCALL
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;CHECK-NEXT: .Lfunc_end0:
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;CHECK-LABLE: __regcall3__func:
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;CHECK: addl $_GLOBAL_OFFSET_TABLE_+({{.*}}), %ecx
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;CHECK-NEXT: movl a0@GOT(%ecx), %ecx
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;CHECK-NEXT: movl %eax, (%ecx)
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;CHECK-NEXT: retl
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;CHECK-NEXT: .Lfunc_end1:
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