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https://github.com/RPCS3/llvm-mirror.git
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975ba80e31
As discussed on D92645, we don't do a good job of recognising when we don't require the full width of a ymm/zmm build vector because the upper elements are undef/zero. This commit allows us to make use of implicit zeroing of upper elements with AVX instructions, which we emulate in DAG with a INSERT_SUBVECTOR into the bottom of a undef/zero vector of the original type. This exposed a limitation in getTargetConstantBitsFromNode which didn't extract bits from INSERT_SUBVECTORs of different element widths which I've included as well to prevent a couple of regressions.
202 lines
6.2 KiB
LLVM
202 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512
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define <4 x i32> @test1(<8 x i32> %v) {
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; SSE2-LABEL: test1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: test1:
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; AVX: # %bb.0:
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; AVX-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%x = sext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%t = trunc <4 x i64> %s to <4 x i32>
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ret <4 x i32> %t
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}
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define <4 x i32> @test2(<8 x i32> %v) {
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; SSE2-LABEL: test2:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: test2:
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; AVX: # %bb.0:
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%x = sext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%t = trunc <4 x i64> %s to <4 x i32>
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ret <4 x i32> %t
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}
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define <2 x i32> @test3(<8 x i32> %v) {
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; SSE2-LABEL: test3:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: test3:
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; AVX: # %bb.0:
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%x = sext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <2 x i32> <i32 4, i32 5>
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%t = trunc <2 x i64> %s to <2 x i32>
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ret <2 x i32> %t
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}
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define <2 x i32> @test4(<8 x i32> %v) {
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; SSE2-LABEL: test4:
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; SSE2: # %bb.0:
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: test4:
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; AVX: # %bb.0:
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; AVX-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%x = sext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
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%t = trunc <2 x i64> %s to <2 x i32>
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ret <2 x i32> %t
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}
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define <2 x i32> @test5(<8 x i32> %v) {
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; SSE2-LABEL: test5:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: retq
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;
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; AVX2-LABEL: test5:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [3,4,4,4]
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test5:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpmovsxdq %ymm0, %zmm0
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; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512-NEXT: vpextrq $1, %xmm1, %rax
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; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm0
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; AVX512-NEXT: vmovq %xmm0, %rcx
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; AVX512-NEXT: vmovd %eax, %xmm0
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; AVX512-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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%x = sext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <2 x i32> <i32 3, i32 4>
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%t = trunc <2 x i64> %s to <2 x i32>
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ret <2 x i32> %t
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}
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define <4 x i32> @test6(<8 x i32> %v) {
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; SSE2-LABEL: test6:
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; SSE2: # %bb.0:
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: test6:
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; AVX: # %bb.0:
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; AVX-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%x = zext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%t = trunc <4 x i64> %s to <4 x i32>
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ret <4 x i32> %t
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}
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define <4 x i32> @test7(<8 x i32> %v) {
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; SSE2-LABEL: test7:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: test7:
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; AVX: # %bb.0:
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%x = zext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%t = trunc <4 x i64> %s to <4 x i32>
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ret <4 x i32> %t
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}
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define <2 x i32> @test8(<8 x i32> %v) {
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; SSE2-LABEL: test8:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: test8:
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; AVX: # %bb.0:
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; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%x = zext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <2 x i32> <i32 4, i32 5>
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%t = trunc <2 x i64> %s to <2 x i32>
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ret <2 x i32> %t
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}
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define <2 x i32> @test9(<8 x i32> %v) {
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; SSE2-LABEL: test9:
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; SSE2: # %bb.0:
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; SSE2-NEXT: retq
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;
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; AVX-LABEL: test9:
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; AVX: # %bb.0:
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; AVX-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%x = zext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <2 x i32> <i32 0, i32 1>
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%t = trunc <2 x i64> %s to <2 x i32>
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ret <2 x i32> %t
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}
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define <2 x i32> @test10(<8 x i32> %v) {
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; SSE2-LABEL: test10:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: retq
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;
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; AVX2-LABEL: test10:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [3,4,4,4]
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; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
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; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: test10:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpmovzxdq {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero
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; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512-NEXT: vpextrq $1, %xmm1, %rax
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; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm0
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; AVX512-NEXT: vmovq %xmm0, %rcx
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; AVX512-NEXT: vmovd %eax, %xmm0
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; AVX512-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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%x = zext <8 x i32> %v to <8 x i64>
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%s = shufflevector <8 x i64> %x, <8 x i64> undef, <2 x i32> <i32 3, i32 4>
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%t = trunc <2 x i64> %s to <2 x i32>
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ret <2 x i32> %t
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}
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