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0caa8a6b4a
llvm-mirror/lib/Target/AArch64
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Craig Topper 0caa8a6b4a [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. 
For the most part this simplifies all callers. There were two places in X86 that needed an explicit makeArrayRef to shorten a statically sized array.

llvm-svn: 274337
2016-07-01 06:54:47 +00:00
..
AsmParser AArch64: allow MOV (imm) alias to be printed 2016-06-16 01:42:25 +00:00
Disassembler Untabify. 2016-06-20 00:37:41 +00:00
InstPrinter AArch64: allow MOV (imm) alias to be printed 2016-06-16 01:42:25 +00:00
MCTargetDesc Delete MCCodeGenInfo. 2016-06-30 18:25:11 +00:00
TargetInfo Remove autoconf support 2016-01-26 21:29:08 +00:00
Utils Apply most suggestions of clang-tidy's performance-unnecessary-value-param 2016-06-08 19:09:22 +00:00
AArch64.h AArch64: avoid clobbering SP for dead MOVimm pseudos. 2016-04-01 23:14:52 +00:00
AArch64.td [AArch64] Add Broadcom Vulcan scheduling model. 2016-06-30 06:42:31 +00:00
AArch64A53Fix835769.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
AArch64A57FPLoadBalancing.cpp AArch64: Do not test for CPUs, use SubtargetFeatures 2016-06-02 18:03:53 +00:00
AArch64AddressTypePromotion.cpp Cleanup comments. NFC. 2016-05-02 14:50:30 +00:00
AArch64AdvSIMDScalarPass.cpp Add optimization bisect opt-in calls for AArch64 passes 2016-04-25 21:58:52 +00:00
AArch64AsmPrinter.cpp Delete more dead code. 2016-06-22 12:44:16 +00:00
AArch64BranchRelaxation.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
AArch64CallingConvention.h Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef. 2015-12-05 07:13:35 +00:00
AArch64CallingConvention.td AArch64: Use a callee save registers for swiftself parameters 2016-04-13 21:43:16 +00:00
AArch64CallLowering.cpp [GlobalISel] Coding style and whitespace fixes 2016-04-14 17:23:33 +00:00
AArch64CallLowering.h [GlobalISel] Coding style and whitespace fixes 2016-04-14 17:23:33 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp Add optimization bisect opt-in calls for AArch64 passes 2016-04-25 21:58:52 +00:00
AArch64CollectLOH.cpp Add optimization bisect opt-in calls for AArch64 passes 2016-04-25 21:58:52 +00:00
AArch64ConditionalCompares.cpp [AArch64] Remove unused MBP headers/dependency. NFC. 2016-05-05 20:58:38 +00:00
AArch64ConditionOptimizer.cpp Add optimization bisect opt-in calls for AArch64 passes 2016-04-25 21:58:52 +00:00
AArch64DeadRegisterDefinitionsPass.cpp Add optimization bisect opt-in calls for AArch64 passes 2016-04-25 21:58:52 +00:00
AArch64ExpandPseudoInsts.cpp Move helper classes into anonymous namespaces. NFC. 2016-05-15 15:18:11 +00:00
AArch64FastISel.cpp Delete AArch64II::MO_CONSTPOOL. 2016-05-31 18:31:14 +00:00
AArch64FrameLowering.cpp Pass DebugLoc and SDLoc by const ref. 2016-06-12 15:39:02 +00:00
AArch64FrameLowering.h [PEI, AArch64] Use empty spaces in stack area for local stack slot allocation. 2016-06-02 16:22:07 +00:00
AArch64InstrAtomics.td AArch64: expand cmpxchg after regalloc at -O0. 2016-04-14 17:03:29 +00:00
AArch64InstrFormats.td add support for -print-imm-hex for AArch64 2016-05-13 18:00:09 +00:00
AArch64InstrInfo.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
AArch64InstrInfo.h CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
AArch64InstrInfo.td RAS extensions are part of ARMv8.2-A. This change enables them by introducing a 2016-06-03 14:03:27 +00:00
AArch64ISelDAGToDAG.cpp [AArch64] Remove an overly aggressive assert. 2016-06-22 19:18:52 +00:00
AArch64ISelLowering.cpp [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. 2016-07-01 06:54:47 +00:00
AArch64ISelLowering.h CodeGen: Use MachineInstr& in TargetLowering, NFC 2016-06-30 22:52:52 +00:00
AArch64LoadStoreOptimizer.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
AArch64MachineFunctionInfo.h [PEI, AArch64] Use empty spaces in stack area for local stack slot allocation. 2016-06-02 16:22:07 +00:00
AArch64MCInstLower.cpp Convert some AArch64 code to foreach loops. NFC. 2015-08-03 19:04:32 +00:00
AArch64MCInstLower.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
AArch64PBQPRegAlloc.cpp CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC 2016-02-27 06:40:41 +00:00
AArch64PBQPRegAlloc.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp Delete more dead code. 2016-06-22 12:44:16 +00:00
AArch64RedundantCopyElimination.cpp Add optimization bisect opt-in calls for AArch64 passes 2016-04-25 21:58:52 +00:00
AArch64RegisterBankInfo.cpp [AArch64][RegisterBankInfo] G_OR are fine on either GPR or FPR. 2016-06-08 16:53:32 +00:00
AArch64RegisterBankInfo.h [AArch64][RegisterBankInfo] G_OR are fine on either GPR or FPR. 2016-06-08 16:53:32 +00:00
AArch64RegisterInfo.cpp AArch64: Remove unnecessary namespace llvm; NFC 2016-06-28 00:54:33 +00:00
AArch64RegisterInfo.h CXX_FAST_TLS calling convention: performance improvement for AArch64. 2015-12-16 21:04:19 +00:00
AArch64RegisterInfo.td Fix typo in comment. NFC 2016-04-24 17:55:57 +00:00
AArch64SchedA53.td Remove MinLatency in SchedMachineModel. NFC. 2016-04-26 00:37:46 +00:00
AArch64SchedA57.td AArch64: Reenable CompleteModel for A53, A57 and Kryo models 2016-03-01 21:55:35 +00:00
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
AArch64SchedKryo.td AArch64: Reenable CompleteModel for A53, A57 and Kryo models 2016-03-01 21:55:35 +00:00
AArch64SchedKryoDetails.td [AArch64] Add support for Qualcomm Kryo CPU. 2016-02-12 15:51:51 +00:00
AArch64SchedM1.td [AArch64] Adjust the model for the vector by element FP multiplies on Exynos M1. (NFC) 2016-06-24 18:58:54 +00:00
AArch64Schedule.td CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
AArch64SchedVulcan.td [AArch64] Add Broadcom Vulcan scheduling model. 2016-06-30 06:42:31 +00:00
AArch64SelectionDAGInfo.cpp [SDAG] Remove FixedArgs parameter from CallLoweringInfo::setCallee 2016-06-22 12:54:25 +00:00
AArch64SelectionDAGInfo.h Pass DebugLoc and SDLoc by const ref. 2016-06-12 15:39:02 +00:00
AArch64StorePairSuppress.cpp CodeGen: Use MachineInstr& in TargetInstrInfo, NFC 2016-06-30 00:01:54 +00:00
AArch64Subtarget.cpp Target: Remove unused arguments from overrideSchedPolicy, NFC 2016-07-01 00:23:27 +00:00
AArch64Subtarget.h Target: Remove unused arguments from overrideSchedPolicy, NFC 2016-07-01 00:23:27 +00:00
AArch64TargetMachine.cpp [AArch64] Change the preferred alignment for char and short to word alignment 2016-06-21 15:55:18 +00:00
AArch64TargetMachine.h Delete Reloc::Default. 2016-05-18 22:04:49 +00:00
AArch64TargetObjectFile.cpp MC: Clean up MCExpr naming. NFC. 2015-05-30 01:25:56 +00:00
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp AArch64: Do not test for CPUs, use SubtargetFeatures 2016-06-02 18:03:53 +00:00
AArch64TargetTransformInfo.h [TTI] Add hook for vector extract with extension 2016-04-27 15:20:21 +00:00
CMakeLists.txt [AArch64][CallLowering] Do not build the API if GlobalISel is not built. 2016-04-07 20:47:51 +00:00
LLVMBuild.txt [AArch64] Plug the beginning of the GlobalISel pipeline. 2016-02-11 19:35:06 +00:00