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231 lines
8.9 KiB
C++
231 lines
8.9 KiB
C++
//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86ISELLOWERING_H
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#define X86ISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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namespace llvm {
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namespace X86ISD {
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// X86 Specific DAG Nodes
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enum NodeType {
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// Start the numbering where the builtin ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
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/// ADD_FLAG, SUB_FLAG - Same as ISD::ADD and ISD::SUB except it also
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/// produces a flag result.
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ADD_FLAG,
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SUB_FLAG,
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/// ADC, SBB - Add with carry and subtraction with borrow. These
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/// correspond to X86::ADCxx and X86::SBBxx instructions.
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ADC,
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SBB,
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/// SHLD, SHRD - Double shift instructions. These correspond to
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/// X86::SHLDxx and X86::SHRDxx instructions.
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SHLD,
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SHRD,
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/// FILD64m - This instruction implements SINT_TO_FP with a
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/// 64-bit source in memory and a FP reg result. This corresponds to
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/// the X86::FILD64m instruction. It has two inputs (token chain and
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/// address) and two outputs (FP value and token chain).
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FILD64m,
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/// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
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/// integer destination in memory and a FP reg source. This corresponds
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/// to the X86::FIST*m instructions and the rounding mode change stuff. It
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/// has two inputs (token chain and address) and two outputs (FP value and
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/// token chain).
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FP_TO_INT16_IN_MEM,
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FP_TO_INT32_IN_MEM,
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FP_TO_INT64_IN_MEM,
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/// FLD - This instruction implements an extending load to FP stack slots.
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/// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
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/// operand, ptr to load from, and a ValueType node indicating the type
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/// to load to.
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FLD,
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/// FST - This instruction implements a truncating store to FP stack
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/// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
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/// chain operand, value to store, address, and a ValueType to store it
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/// as.
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FST,
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/// FP_SET_RESULT - This corresponds to FpGETRESULT pseudo instrcuction
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/// which copies from ST(0) to the destination. It takes a chain and writes
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/// a RFP result and a chain.
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FP_GET_RESULT,
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/// FP_SET_RESULT - This corresponds to FpSETRESULT pseudo instrcuction
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/// which copies the source operand to ST(0). It takes a chain and writes
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/// a chain and a flag.
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FP_SET_RESULT,
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/// CALL/TAILCALL - These operations represent an abstract X86 call
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/// instruction, which includes a bunch of information. In particular the
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/// operands of these node are:
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///
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/// #0 - The incoming token chain
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/// #1 - The callee
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/// #2 - The number of arg bytes the caller pushes on the stack.
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/// #3 - The number of arg bytes the callee pops off the stack.
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/// #4 - The value to pass in AL/AX/EAX (optional)
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/// #5 - The value to pass in DL/DX/EDX (optional)
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///
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/// The result values of these nodes are:
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///
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/// #0 - The outgoing token chain
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/// #1 - The first register result value (optional)
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/// #2 - The second register result value (optional)
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///
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/// The CALL vs TAILCALL distinction boils down to whether the callee is
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/// known not to modify the caller's stack frame, as is standard with
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/// LLVM.
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CALL,
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TAILCALL,
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/// RDTSC_DAG - This operation implements the lowering for
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/// readcyclecounter
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RDTSC_DAG,
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/// X86 compare and logical compare instructions.
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CMP, TEST,
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/// X86 SetCC. Operand 1 is condition code, and operand 2 is the flag
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/// operand produced by a CMP instruction.
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SETCC,
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/// X86 conditional moves. Operand 1 and operand 2 are the two values
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/// to select from (operand 1 is a R/W operand). Operand 3 is the condition
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/// code, and operand 4 is the flag operand produced by a CMP or TEST
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/// instruction. It also writes a flag result.
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CMOV,
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/// X86 conditional branches. Operand 1 is the chain operand, operand 2
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/// is the block to branch if condition is true, operand 3 is the
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/// condition code, and operand 4 is the flag operand produced by a CMP
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/// or TEST instruction.
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BRCOND,
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/// Return with a flag operand. Operand 1 is the number of bytes of stack
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/// to pop, operand 2 is the chain and operand 3 is a flag operand.
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RET_FLAG,
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};
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// X86 specific condition code. These correspond to X86_*_COND in
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// X86InstrInfo.td. They must be kept in synch.
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enum CondCode {
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COND_A = 0,
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COND_AE = 1,
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COND_B = 2,
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COND_BE = 3,
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COND_E = 4,
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COND_G = 5,
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COND_GE = 6,
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COND_L = 7,
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COND_LE = 8,
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COND_NE = 9,
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COND_NO = 10,
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COND_NP = 11,
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COND_NS = 12,
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COND_O = 13,
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COND_P = 14,
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COND_S = 15,
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COND_INVALID
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};
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}
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//===----------------------------------------------------------------------===//
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// X86TargetLowering - X86 Implementation of the TargetLowering interface
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class X86TargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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int ReturnAddrIndex; // FrameIndex for return slot.
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int BytesToPopOnReturn; // Number of arg bytes ret should pop.
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int BytesCallerReserves; // Number of arg bytes caller makes.
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public:
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X86TargetLowering(TargetMachine &TM);
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// Return the number of bytes that a function should pop when it returns (in
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// addition to the space used by the return address).
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//
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unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
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// Return the number of bytes that the caller reserves for arguments passed
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// to this function.
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unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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/// LowerArguments - This hook must be implemented to indicate how we should
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/// lower the arguments for the specified function, into the specified DAG.
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virtual std::vector<SDOperand>
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LowerArguments(Function &F, SelectionDAG &DAG);
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// actual call.
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
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SelectionDAG &DAG);
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virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG);
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virtual std::pair<SDOperand,SDOperand>
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LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
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const Type *ArgTy, SelectionDAG &DAG);
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virtual std::pair<SDOperand, SDOperand>
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LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
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SelectionDAG &DAG);
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/// getTargetNodeName - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
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/// be zero. Op is expected to be a target specific node. Used by DAG
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/// combiner.
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virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
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uint64_t Mask) const;
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SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
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private:
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// C Calling Convention implementation.
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std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);
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std::pair<SDOperand, SDOperand>
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LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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bool isTailCall,
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SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
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// Fast Calling Convention implementation.
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std::vector<SDOperand> LowerFastCCArguments(Function &F, SelectionDAG &DAG);
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std::pair<SDOperand, SDOperand>
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LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, bool isTailCall,
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SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
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};
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}
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#endif // X86ISELLOWERING_H
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