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llvm-mirror/utils/TableGen
Krzysztof Parzyszek 49652486ed [TableGen] Examine entire subreg compositions to detect ambiguity
When tablegen detects that there exist two subregister compositions that
result in the same value for some register, it will emit a warning. This
kind of an overlap in compositions should only happen when it is caused
by a user-defined composition. It can happen, however, that the user-
defined composition is not identically equal to another one, but it does
produce the same value for one or more registers. In such cases suppress
the warning.
This patch is to silence the warning when building the System Z backend
after D50725.

Differential Revision: https://reviews.llvm.org/D50977

llvm-svn: 347894
2018-11-29 18:20:08 +00:00
..
AsmMatcherEmitter.cpp Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC 2018-10-19 06:12:02 +00:00
AsmWriterEmitter.cpp [TableGen] Prevent double flattening of InstAlias asm strings in the asm matcher emitter. 2018-06-18 01:28:01 +00:00
AsmWriterInst.cpp
AsmWriterInst.h
Attributes.cpp
CallingConvEmitter.cpp
CMakeLists.txt [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel. 2018-10-25 07:44:01 +00:00
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp TableGen/CodeGenDAGPatterns: addPredicateFn only once 2018-10-08 16:53:31 +00:00
CodeGenDAGPatterns.h TableGen/CodeGenDAGPatterns: addPredicateFn only once 2018-10-08 16:53:31 +00:00
CodeGenHwModes.cpp
CodeGenHwModes.h
CodeGenInstruction.cpp [TableGen] Better error checking for TIED_TO constraints. 2018-11-28 11:43:49 +00:00
CodeGenInstruction.h Fix -Winfinite-recursion compile error. 2018-11-28 12:32:53 +00:00
CodeGenIntrinsics.h Mark @llvm.trap cold 2018-11-14 19:53:41 +00:00
CodeGenMapTable.cpp
CodeGenRegisters.cpp [TableGen] Examine entire subreg compositions to detect ambiguity 2018-11-29 18:20:08 +00:00
CodeGenRegisters.h [TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum 2018-08-16 15:29:24 +00:00
CodeGenSchedule.cpp [llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666). 2018-11-29 12:15:56 +00:00
CodeGenSchedule.h [llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666). 2018-11-29 12:15:56 +00:00
CodeGenTarget.cpp Mark @llvm.trap cold 2018-11-14 19:53:41 +00:00
CodeGenTarget.h
CTagsEmitter.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
DAGISelEmitter.cpp [TableGen] Support multi-alternative pattern fragments 2018-07-13 13:18:00 +00:00
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp [TableGen] Return ValueTypeByHwMode by const reference from CodeGenRegisterClass::getValueTypeNum 2018-08-16 15:29:24 +00:00
DAGISelMatcherOpt.cpp
DFAPacketizerEmitter.cpp
DisassemblerEmitter.cpp
ExegesisEmitter.cpp [llvm-exegesis][NFC] Add a way to declare the default counter binding for unbound CPUs for a target. 2018-11-09 13:15:32 +00:00
FastISelEmitter.cpp Use the container form llvm::sort(C, ...) 2018-09-30 22:31:29 +00:00
FixedLenDecoderEmitter.cpp Fix MSVC build by correcting placement of declspec after r345056 2018-10-23 17:41:39 +00:00
GlobalISelEmitter.cpp Use the container form llvm::sort(C, ...) 2018-09-30 22:31:29 +00:00
InfoByHwMode.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
InfoByHwMode.h [TableGen] Don't separately search for DefaultMode when we're going to iterate the set anyway. NFCI. 2018-08-17 17:45:15 +00:00
InstrDocsEmitter.cpp [WebAssembly] Add isEHScopeReturn instruction property 2018-08-21 19:44:11 +00:00
InstrInfoEmitter.cpp [TableGen] Refactor macro names (NFC) 2018-11-27 20:58:27 +00:00
IntrinsicEmitter.cpp Mark @llvm.trap cold 2018-11-14 19:53:41 +00:00
LLVMBuild.txt
OptParserEmitter.cpp
PredicateExpander.cpp [TableGen] Improve readability of generated code (NFC) 2018-11-27 20:59:01 +00:00
PredicateExpander.h [tblgen][PredicateExpander] Add the ability to describe more complex constraints on instruction operands. 2018-10-31 12:28:05 +00:00
PseudoLoweringEmitter.cpp
RegisterBankEmitter.cpp
RegisterInfoEmitter.cpp Use the container form llvm::sort(C) 2018-10-31 00:31:06 +00:00
RISCVCompressInstEmitter.cpp
SDNodeProperties.cpp
SDNodeProperties.h
SearchableTableEmitter.cpp TableGen: Fix ASAN error 2018-10-31 17:46:21 +00:00
SequenceToOffsetTable.h
SubtargetEmitter.cpp [llvm-mca][MC] Add the ability to declare which processor resources model load/store queues (PR36666). 2018-11-29 12:15:56 +00:00
SubtargetFeatureInfo.cpp
SubtargetFeatureInfo.h
TableGen.cpp [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel. 2018-10-25 07:44:01 +00:00
TableGenBackends.h [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel. 2018-10-25 07:44:01 +00:00
tdtags
Types.cpp
Types.h
WebAssemblyDisassemblerEmitter.cpp [WebAssembly] Read prefixed opcodes as ULEB128s 2018-11-09 01:57:00 +00:00
WebAssemblyDisassemblerEmitter.h
X86DisassemblerShared.h
X86DisassemblerTables.cpp
X86DisassemblerTables.h
X86EVEX2VEXTablesEmitter.cpp [X86] Add the ability to force an EVEX2VEX mapping table entry from the .td files. Remove remaining manual table entries from the tablegen emitter. 2018-06-19 04:24:44 +00:00
X86FoldTablesEmitter.cpp [X86] More additions to the load folding tables based on the autogenerated tables. 2018-06-16 23:25:50 +00:00
X86ModRMFilters.cpp
X86ModRMFilters.h Test commit: remove trailing whitespace 2018-09-11 17:28:43 +00:00
X86RecognizableInstr.cpp [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions. 2018-08-13 22:06:28 +00:00
X86RecognizableInstr.h [X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0. 2018-06-19 04:24:42 +00:00