Nemanja Ivanovic 3f9ad6b478 [PowerPC] Recommit r314244 with refactoring and off by default ... This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434		2017-11-30 13:39:10 +00:00
..
AArch64	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
AMDGPU	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
ARC
ARM	[ARM GlobalISel] Bail out for byval	2017-11-30 12:23:44 +00:00
AVR	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
BPF	[CodeGen] Print register names in lowercase in both MIR and debug output	2017-11-28 17:15:09 +00:00
Generic	Support generic lowering of vector bswap	2017-11-30 11:06:22 +00:00
Hexagon	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
Inputs
Lanai	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
Mips	[CodeGen] Print register names in lowercase in both MIR and debug output	2017-11-28 17:15:09 +00:00
MIR	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
MSP430
Nios2
NVPTX
PowerPC	[PowerPC] Recommit r314244 with refactoring and off by default	2017-11-30 13:39:10 +00:00
RISCV
SPARC
SystemZ	[SystemZ] Bugfix in adjustSubwordCmp.	2017-11-30 08:18:50 +00:00
Thumb
Thumb2
WebAssembly	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
WinEH
X86	[X86][AVX512] Tag fcmp/ptest/ternlog instructions scheduler classes	2017-11-30 13:18:06 +00:00
XCore