Alex Bradbury 43a1fee3ed [RISCV] Use register X0 (ZERO) for constant 0 ... The obvious approach of defining a pattern like the one below actually doesn't work: `def : Pat<(i32 0), (i32 X0)>;` As was noted when Lanai made this change (https://reviews.llvm.org/rL288215), attempting to handle the constant 0 in tablegen leads to assertions due to a physical register being used where a virtual register is expected. llvm-svn: 318738		2017-11-21 08:23:08 +00:00
..
addc-adde-sube-subc.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
alu32.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
bare-select.ll	[RISCV] Use register X0 (ZERO) for constant 0	2017-11-21 08:23:08 +00:00
blockaddress.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
branch.ll	[RISCV] Codegen for conditional branches	2017-11-08 13:31:40 +00:00
bswap-ctlz-cttz-ctpop.ll	[RISCV] Use register X0 (ZERO) for constant 0	2017-11-21 08:23:08 +00:00
calls.ll	[RISCV] Initial support for function calls	2017-11-08 13:41:21 +00:00
div.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
i32-icmp.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
imm.ll
indirectbr.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
jumptable.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
lit.local.cfg
mem.ll	[RISCV] Codegen support for memory operations on global addresses	2017-11-08 13:24:21 +00:00
mul.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
rem.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
rotl-rotr.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
select-cc.ll	[RISCV] Implement lowering of ISD::SELECT	2017-11-21 07:51:32 +00:00
sext-zext-trunc.ll	[RISCV] Use register X0 (ZERO) for constant 0	2017-11-21 08:23:08 +00:00
shifts.ll	[RISCV] Support and tests for a variety of additional LLVM IR constructs	2017-11-21 08:11:03 +00:00
wide-mem.ll	[RISCV] Codegen support for memory operations on global addresses	2017-11-08 13:24:21 +00:00