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cc724f15ca
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
31 lines
866 B
LLVM
31 lines
866 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
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define i64 @addc_adde(i64 %a, i64 %b) {
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; RV32I-LABEL: addc_adde:
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; RV32I: # BB#0:
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; RV32I-NEXT: add a1, a1, a3
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; RV32I-NEXT: add a2, a0, a2
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: add a1, a1, a0
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; RV32I-NEXT: addi a0, a2, 0
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = add i64 %a, %b
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ret i64 %1
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}
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define i64 @subc_sube(i64 %a, i64 %b) {
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; RV32I-LABEL: subc_sube:
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; RV32I: # BB#0:
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: sltu a3, a0, a2
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; RV32I-NEXT: sub a1, a1, a3
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; RV32I-NEXT: sub a0, a0, a2
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sub i64 %a, %b
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ret i64 %1
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}
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