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cc724f15ca
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
llvm-svn: 318737
187 lines
4.0 KiB
LLVM
187 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; These tests are each targeted at a particular RISC-V ALU instruction. Other
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; files in this folder exercise LLVM IR instructions that don't directly match a
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; RISC-V instruction
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; Register-immediate instructions
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define i32 @addi(i32 %a) nounwind {
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; RV32I-LABEL: addi:
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; RV32I: # BB#0:
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = add i32 %a, 1
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ret i32 %1
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}
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define i32 @slti(i32 %a) nounwind {
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; RV32I-LABEL: slti:
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; RV32I: # BB#0:
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; RV32I-NEXT: slti a0, a0, 2
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = icmp slt i32 %a, 2
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @sltiu(i32 %a) nounwind {
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; RV32I-LABEL: sltiu:
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; RV32I: # BB#0:
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; RV32I-NEXT: sltiu a0, a0, 3
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = icmp ult i32 %a, 3
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @xori(i32 %a) nounwind {
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; RV32I-LABEL: xori:
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; RV32I: # BB#0:
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; RV32I-NEXT: xori a0, a0, 4
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = xor i32 %a, 4
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ret i32 %1
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}
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define i32 @ori(i32 %a) nounwind {
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; RV32I-LABEL: ori:
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; RV32I: # BB#0:
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; RV32I-NEXT: ori a0, a0, 5
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = or i32 %a, 5
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ret i32 %1
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}
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define i32 @andi(i32 %a) nounwind {
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; RV32I-LABEL: andi:
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; RV32I: # BB#0:
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; RV32I-NEXT: andi a0, a0, 6
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = and i32 %a, 6
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ret i32 %1
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}
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define i32 @slli(i32 %a) nounwind {
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; RV32I-LABEL: slli:
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; RV32I: # BB#0:
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; RV32I-NEXT: slli a0, a0, 7
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = shl i32 %a, 7
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ret i32 %1
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}
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define i32 @srli(i32 %a) nounwind {
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; RV32I-LABEL: srli:
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; RV32I: # BB#0:
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; RV32I-NEXT: srli a0, a0, 8
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = lshr i32 %a, 8
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ret i32 %1
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}
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define i32 @srai(i32 %a) nounwind {
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; RV32I-LABEL: srai:
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; RV32I: # BB#0:
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; RV32I-NEXT: srai a0, a0, 9
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = ashr i32 %a, 9
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ret i32 %1
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}
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; Register-register instructions
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define i32 @add(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: add:
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; RV32I: # BB#0:
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = add i32 %a, %b
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ret i32 %1
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}
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define i32 @sub(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sub:
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; RV32I: # BB#0:
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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define i32 @sll(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sll:
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; RV32I: # BB#0:
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; RV32I-NEXT: sll a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = shl i32 %a, %b
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ret i32 %1
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}
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define i32 @slt(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: slt:
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; RV32I: # BB#0:
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; RV32I-NEXT: slt a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = icmp slt i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @sltu(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sltu:
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; RV32I: # BB#0:
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = icmp ult i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @xor(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: xor:
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; RV32I: # BB#0:
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = xor i32 %a, %b
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ret i32 %1
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}
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define i32 @srl(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: srl:
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; RV32I: # BB#0:
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; RV32I-NEXT: srl a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = lshr i32 %a, %b
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ret i32 %1
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}
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define i32 @sra(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: sra:
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; RV32I: # BB#0:
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; RV32I-NEXT: sra a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = ashr i32 %a, %b
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ret i32 %1
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}
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define i32 @or(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: or:
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; RV32I: # BB#0:
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = or i32 %a, %b
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ret i32 %1
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}
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define i32 @and(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: and:
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; RV32I: # BB#0:
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: jalr zero, ra, 0
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%1 = and i32 %a, %b
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ret i32 %1
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}
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