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3bda78713b
Add selection support for ext via a new opcode, G_EXT and a post-legalizer combine which matches it. Add an `applyEXT` function, because the AArch64ext patterns require a register for the immediate. So, we have to create a G_CONSTANT to get these without writing new patterns or modifying the existing ones. Tests are the same as arm64-ext.ll. Also prevent ext from firing on the zip test. It has higher priority, so we don't want it potentially getting in the way of mask tests. Also fix up the shuffle-splat test, because ext is now selected there. The test was incorrectly regbank selected before, which could cause a verifier failure when you emit copies. Differential Revision: https://reviews.llvm.org/D81436
125 lines
4.3 KiB
TableGen
125 lines
4.3 KiB
TableGen
//=----- AArch64InstrGISel.td - AArch64 GISel target pseudos -*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 GlobalISel target pseudo instruction definitions. This is kept
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// separately from the other tablegen files for organizational purposes, but
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// share the same infrastructure.
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//
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//===----------------------------------------------------------------------===//
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class AArch64GenericInstruction : GenericInstruction {
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let Namespace = "AArch64";
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}
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// A pseudo to represent a relocatable add instruction as part of address
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// computation.
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def G_ADD_LOW : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type1:$src, type2:$imm);
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let hasSideEffects = 0;
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}
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// Pseudo for a rev16 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_REV16 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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// Pseudo for a rev32 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_REV32 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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// Pseudo for a rev64 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_REV64 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$src);
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let hasSideEffects = 0;
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}
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// Represents an uzp1 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_UZP1 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents an uzp2 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_UZP2 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents a zip1 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_ZIP1 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents a zip2 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_ZIP2 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents a dup instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_DUP: AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type1:$lane);
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let hasSideEffects = 0;
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}
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// Represents a trn1 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_TRN1 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents a trn2 instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_TRN2 : AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2);
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let hasSideEffects = 0;
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}
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// Represents an ext instruction. Produced post-legalization from
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// G_SHUFFLE_VECTORs with appropriate masks.
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def G_EXT: AArch64GenericInstruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm);
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}
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def : GINodeEquiv<G_REV16, AArch64rev16>;
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def : GINodeEquiv<G_REV32, AArch64rev32>;
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def : GINodeEquiv<G_REV64, AArch64rev64>;
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def : GINodeEquiv<G_UZP1, AArch64uzp1>;
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def : GINodeEquiv<G_UZP2, AArch64uzp2>;
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def : GINodeEquiv<G_ZIP1, AArch64zip1>;
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def : GINodeEquiv<G_ZIP2, AArch64zip2>;
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def : GINodeEquiv<G_DUP, AArch64dup>;
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def : GINodeEquiv<G_TRN1, AArch64trn1>;
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def : GINodeEquiv<G_TRN2, AArch64trn2>;
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def : GINodeEquiv<G_EXT, AArch64ext>;
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