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Stage 2: added detailed description of operands See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572 llvm-svn: 349368
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23 lines
897 B
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* Automatically generated file, do not edit! *
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.. _amdgpu_synid9_dst_mimg_regular_d16:
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vdst
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===========================
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Image data to load by an image instruction.
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*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
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* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
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* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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