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https://github.com/RPCS3/llvm-mirror.git
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5efe040582
Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
659 lines
18 KiB
LLVM
659 lines
18 KiB
LLVM
; RUN: llc < %s -mcpu=cyclone -verify-machineinstrs -aarch64-enable-ccmp -aarch64-stress-ccmp | FileCheck %s
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target triple = "arm64-apple-ios"
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; CHECK: single_same
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; CHECK: cmp w0, #5
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; CHECK-NEXT: ccmp w1, #17, #4, ne
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; CHECK-NEXT: b.ne
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; CHECK: %if.then
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; CHECK: bl _foo
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; CHECK: %if.end
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define i32 @single_same(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 5
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%cmp1 = icmp eq i32 %b, 17
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Different condition codes for the two compares.
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; CHECK: single_different
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; CHECK: cmp w0, #6
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; CHECK-NEXT: ccmp w1, #17, #0, ge
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; CHECK-NEXT: b.eq
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; CHECK: %if.then
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; CHECK: bl _foo
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; CHECK: %if.end
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define i32 @single_different(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp sle i32 %a, 5
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%cmp1 = icmp ne i32 %b, 17
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Second block clobbers the flags, can't convert (easily).
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; CHECK: single_flagclobber
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; CHECK: cmp
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; CHECK: b.eq
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; CHECK: cmp
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; CHECK: b.gt
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define i32 @single_flagclobber(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 5
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br i1 %cmp, label %if.then, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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%cmp1 = icmp slt i32 %b, 7
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%mul = shl nsw i32 %b, 1
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%add = add nsw i32 %b, 1
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%cond = select i1 %cmp1, i32 %mul, i32 %add
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%cmp2 = icmp slt i32 %cond, 17
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br i1 %cmp2, label %if.then, label %if.end
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if.then: ; preds = %lor.lhs.false, %entry
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end: ; preds = %if.then, %lor.lhs.false
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ret i32 7
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}
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; Second block clobbers the flags and ends with a tbz terminator.
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; CHECK: single_flagclobber_tbz
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; CHECK: cmp
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; CHECK: b.eq
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; CHECK: cmp
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; CHECK: tbz
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define i32 @single_flagclobber_tbz(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 5
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br i1 %cmp, label %if.then, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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%cmp1 = icmp slt i32 %b, 7
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%mul = shl nsw i32 %b, 1
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%add = add nsw i32 %b, 1
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%cond = select i1 %cmp1, i32 %mul, i32 %add
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%and = and i32 %cond, 8
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%cmp2 = icmp ne i32 %and, 0
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br i1 %cmp2, label %if.then, label %if.end
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if.then: ; preds = %lor.lhs.false, %entry
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end: ; preds = %if.then, %lor.lhs.false
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ret i32 7
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}
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; Speculatively execute division by zero.
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; The sdiv/udiv instructions do not trap when the divisor is zero, so they are
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; safe to speculate.
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; CHECK-LABEL: speculate_division:
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; CHECK: cmp w0, #1
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; CHECK: sdiv [[DIVRES:w[0-9]+]], w1, w0
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; CHECK: ccmp [[DIVRES]], #16, #0, ge
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; CHECK: b.gt [[BLOCK:LBB[0-9_]+]]
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; CHECK: bl _foo
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; CHECK: [[BLOCK]]:
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; CHECK: orr w0, wzr, #0x7
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define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %land.lhs.true, label %if.end
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land.lhs.true:
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%div = sdiv i32 %b, %a
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%cmp1 = icmp slt i32 %div, 17
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br i1 %cmp1, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Floating point compare.
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; CHECK: single_fcmp
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; CHECK: cmp
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; CHECK-NOT: b.
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; CHECK: fccmp {{.*}}, #8, ge
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; CHECK: b.lt
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define i32 @single_fcmp(i32 %a, float %b) nounwind ssp {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %land.lhs.true, label %if.end
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land.lhs.true:
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%conv = sitofp i32 %a to float
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%div = fdiv float %b, %conv
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%cmp1 = fcmp oge float %div, 1.700000e+01
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br i1 %cmp1, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Chain multiple compares.
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; CHECK: multi_different
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; CHECK: cmp
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; CHECK: ccmp
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; CHECK: ccmp
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; CHECK: b.
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define void @multi_different(i32 %a, i32 %b, i32 %c) nounwind ssp {
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entry:
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%cmp = icmp sgt i32 %a, %b
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br i1 %cmp, label %land.lhs.true, label %if.end
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land.lhs.true:
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%div = sdiv i32 %b, %a
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%cmp1 = icmp eq i32 %div, 5
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%cmp4 = icmp sgt i32 %div, %c
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%or.cond = and i1 %cmp1, %cmp4
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret void
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}
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; Convert a cbz in the head block.
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; CHECK: cbz_head
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; CHECK: cmp w0, #0
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; CHECK: ccmp
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define i32 @cbz_head(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp ne i32 %b, 17
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Check that the immediate operand is in range. The ccmp instruction encodes a
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; smaller range of immediates than subs/adds.
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; The ccmp immediates must be in the range 0-31.
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; CHECK: immediate_range
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; CHECK-NOT: ccmp
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define i32 @immediate_range(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 5
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%cmp1 = icmp eq i32 %b, 32
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Convert a cbz in the second block.
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; CHECK: cbz_second
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; CHECK: cmp w0, #0
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; CHECK: ccmp w1, #0, #0, ne
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; CHECK: b.eq
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define i32 @cbz_second(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp ne i32 %b, 0
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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; Convert a cbnz in the second block.
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; CHECK: cbnz_second
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; CHECK: cmp w0, #0
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; CHECK: ccmp w1, #0, #4, ne
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; CHECK: b.ne
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define i32 @cbnz_second(i32 %a, i32 %b) nounwind ssp {
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entry:
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%cmp = icmp eq i32 %a, 0
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%cmp1 = icmp eq i32 %b, 0
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%or.cond = or i1 %cmp, %cmp1
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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%call = tail call i32 @foo() nounwind
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br label %if.end
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if.end:
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ret i32 7
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}
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declare i32 @foo()
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%str1 = type { %str2 }
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%str2 = type { [24 x i8], i8*, i32, %str1*, i32, [4 x i8], %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, i8*, i8, i8*, %str1*, i8* }
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; Test case distilled from 126.gcc.
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; The phi in sw.bb.i.i gets multiple operands for the %entry predecessor.
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; CHECK: build_modify_expr
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define void @build_modify_expr() nounwind ssp {
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entry:
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switch i32 undef, label %sw.bb.i.i [
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i32 69, label %if.end85
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i32 70, label %if.end85
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i32 71, label %if.end85
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i32 72, label %if.end85
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i32 73, label %if.end85
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i32 105, label %if.end85
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i32 106, label %if.end85
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]
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if.end85:
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ret void
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sw.bb.i.i:
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%ref.tr.i.i = phi %str1* [ %0, %sw.bb.i.i ], [ undef, %entry ]
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%operands.i.i = getelementptr inbounds %str1, %str1* %ref.tr.i.i, i64 0, i32 0, i32 2
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%arrayidx.i.i = bitcast i32* %operands.i.i to %str1**
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%0 = load %str1*, %str1** %arrayidx.i.i, align 8
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%code1.i.i.phi.trans.insert = getelementptr inbounds %str1, %str1* %0, i64 0, i32 0, i32 0, i64 16
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br label %sw.bb.i.i
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}
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; CHECK-LABEL: select_and
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define i64 @select_and(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
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; CHECK: cmp w1, #5
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; CHECK-NEXT: ccmp w0, w1, #0, ne
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; CHECK-NEXT: csel x0, x2, x3, lt
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; CHECK-NEXT: ret
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%1 = icmp slt i32 %w0, %w1
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%2 = icmp ne i32 5, %w1
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%3 = and i1 %1, %2
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%sel = select i1 %3, i64 %x2, i64 %x3
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ret i64 %sel
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}
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; CHECK-LABEL: select_or
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define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
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; CHECK: cmp w1, #5
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; CHECK-NEXT: ccmp w0, w1, #8, eq
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; CHECK-NEXT: csel x0, x2, x3, lt
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; CHECK-NEXT: ret
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%1 = icmp slt i32 %w0, %w1
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%2 = icmp ne i32 5, %w1
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%3 = or i1 %1, %2
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%sel = select i1 %3, i64 %x2, i64 %x3
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ret i64 %sel
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}
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; CHECK-LABEL: gccbug
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define i64 @gccbug(i64 %x0, i64 %x1) {
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; CHECK: cmp x0, #2
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; CHECK-NEXT: ccmp x0, #4, #4, ne
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; CHECK-NEXT: ccmp x1, #0, #0, eq
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; CHECK-NEXT: orr w[[REGNUM:[0-9]+]], wzr, #0x1
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; CHECK-NEXT: cinc x0, x[[REGNUM]], eq
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; CHECK-NEXT: ret
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%cmp0 = icmp eq i64 %x1, 0
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%cmp1 = icmp eq i64 %x0, 2
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%cmp2 = icmp eq i64 %x0, 4
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%or = or i1 %cmp2, %cmp1
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%and = and i1 %or, %cmp0
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%sel = select i1 %and, i64 2, i64 1
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ret i64 %sel
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}
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; CHECK-LABEL: select_ororand
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define i32 @select_ororand(i32 %w0, i32 %w1, i32 %w2, i32 %w3) {
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; CHECK: cmp w3, #4
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; CHECK-NEXT: ccmp w2, #2, #0, gt
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; CHECK-NEXT: ccmp w1, #13, #2, ge
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; CHECK-NEXT: ccmp w0, #0, #4, ls
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; CHECK-NEXT: csel w0, w3, wzr, eq
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; CHECK-NEXT: ret
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%c0 = icmp eq i32 %w0, 0
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%c1 = icmp ugt i32 %w1, 13
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%c2 = icmp slt i32 %w2, 2
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%c4 = icmp sgt i32 %w3, 4
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%or = or i1 %c0, %c1
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%and = and i1 %c2, %c4
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%or1 = or i1 %or, %and
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%sel = select i1 %or1, i32 %w3, i32 0
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ret i32 %sel
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}
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; CHECK-LABEL: select_andor
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define i32 @select_andor(i32 %v1, i32 %v2, i32 %v3) {
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; CHECK: cmp w1, w2
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; CHECK-NEXT: ccmp w0, #0, #4, lt
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; CHECK-NEXT: ccmp w0, w1, #0, eq
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; CHECK-NEXT: csel w0, w0, w1, eq
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; CHECK-NEXT: ret
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%c0 = icmp eq i32 %v1, %v2
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%c1 = icmp sge i32 %v2, %v3
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%c2 = icmp eq i32 %v1, 0
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%or = or i1 %c2, %c1
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%and = and i1 %or, %c0
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%sel = select i1 %and, i32 %v1, i32 %v2
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ret i32 %sel
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}
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; CHECK-LABEL: select_noccmp1
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define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
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; CHECK: cmp x0, #0
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; CHECK-NEXT: cset [[REG0:w[0-9]+]], lt
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; CHECK-NEXT: cmp x0, #13
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; CHECK-NOT: ccmp
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; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt
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; CHECK-NEXT: cmp x2, #2
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; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt
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; CHECK-NEXT: cmp x2, #4
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; CHECK-NEXT: cset [[REG3:w[0-9]+]], gt
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; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
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; CHECK-NEXT: and [[REG5:w[0-9]+]], [[REG2]], [[REG3]]
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; CHECK-NEXT: orr [[REG6:w[0-9]+]], [[REG4]], [[REG5]]
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; CHECK-NEXT: cmp [[REG6]], #0
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; CHECK-NEXT: csel x0, xzr, x3, ne
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; CHECK-NEXT: ret
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%c0 = icmp slt i64 %v1, 0
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%c1 = icmp sgt i64 %v1, 13
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%c2 = icmp slt i64 %v3, 2
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%c4 = icmp sgt i64 %v3, 4
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%and0 = and i1 %c0, %c1
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%and1 = and i1 %c2, %c4
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%or = or i1 %and0, %and1
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%sel = select i1 %or, i64 0, i64 %r
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ret i64 %sel
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}
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@g = global i32 0
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; Should not use ccmp if we have to compute the or expression in an integer
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; register anyway because of other users.
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; CHECK-LABEL: select_noccmp2
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define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
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; CHECK: cmp x0, #0
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; CHECK-NEXT: cset [[REG0:w[0-9]+]], lt
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; CHECK-NOT: ccmp
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; CHECK-NEXT: cmp x0, #13
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; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt
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; CHECK-NEXT: orr [[REG2:w[0-9]+]], [[REG0]], [[REG1]]
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; CHECK-NEXT: cmp [[REG2]], #0
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; CHECK-NEXT: csel x0, xzr, x3, ne
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; CHECK-NEXT: sbfx [[REG3:w[0-9]+]], [[REG2]], #0, #1
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; CHECK-NEXT: adrp x[[REGN4:[0-9]+]], _g@PAGE
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; CHECK-NEXT: str [[REG3]], [x[[REGN4]], _g@PAGEOFF]
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; CHECK-NEXT: ret
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%c0 = icmp slt i64 %v1, 0
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%c1 = icmp sgt i64 %v1, 13
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%or = or i1 %c0, %c1
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%sel = select i1 %or, i64 0, i64 %r
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%ext = sext i1 %or to i32
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store volatile i32 %ext, i32* @g
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ret i64 %sel
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}
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; The following is not possible to implement with a single cmp;ccmp;csel
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; sequence.
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; CHECK-LABEL: select_noccmp3
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define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) {
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%c0 = icmp slt i32 %v0, 0
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%c1 = icmp sgt i32 %v0, 13
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%c2 = icmp slt i32 %v0, 22
|
|
%c3 = icmp sgt i32 %v0, 44
|
|
%c4 = icmp eq i32 %v0, 99
|
|
%c5 = icmp eq i32 %v0, 77
|
|
%or0 = or i1 %c0, %c1
|
|
%or1 = or i1 %c2, %c3
|
|
%and0 = and i1 %or0, %or1
|
|
%or2 = or i1 %c4, %c5
|
|
%and1 = and i1 %and0, %or2
|
|
%sel = select i1 %and1, i32 %v1, i32 %v2
|
|
ret i32 %sel
|
|
}
|
|
|
|
; Test the IR CCs that expand to two cond codes.
|
|
|
|
; CHECK-LABEL: select_and_olt_one:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d2, d3, #4, mi
|
|
; CHECK-NEXT: fccmp d2, d3, #1, ne
|
|
; CHECK-NEXT: csel w0, w0, w1, vc
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_and_olt_one(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp olt double %v0, %v1
|
|
%c1 = fcmp one double %v2, %v3
|
|
%cr = and i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: select_and_one_olt:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d0, d1, #1, ne
|
|
; CHECK-NEXT: fccmp d2, d3, #0, vc
|
|
; CHECK-NEXT: csel w0, w0, w1, mi
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_and_one_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp one double %v0, %v1
|
|
%c1 = fcmp olt double %v2, %v3
|
|
%cr = and i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: select_and_olt_ueq:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d2, d3, #0, mi
|
|
; CHECK-NEXT: fccmp d2, d3, #8, le
|
|
; CHECK-NEXT: csel w0, w0, w1, pl
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_and_olt_ueq(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp olt double %v0, %v1
|
|
%c1 = fcmp ueq double %v2, %v3
|
|
%cr = and i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: select_and_ueq_olt:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d0, d1, #8, le
|
|
; CHECK-NEXT: fccmp d2, d3, #0, pl
|
|
; CHECK-NEXT: csel w0, w0, w1, mi
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_and_ueq_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp ueq double %v0, %v1
|
|
%c1 = fcmp olt double %v2, %v3
|
|
%cr = and i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: select_or_olt_one:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d2, d3, #0, pl
|
|
; CHECK-NEXT: fccmp d2, d3, #8, le
|
|
; CHECK-NEXT: csel w0, w0, w1, mi
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_or_olt_one(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp olt double %v0, %v1
|
|
%c1 = fcmp one double %v2, %v3
|
|
%cr = or i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: select_or_one_olt:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d0, d1, #1, ne
|
|
; CHECK-NEXT: fccmp d2, d3, #8, vs
|
|
; CHECK-NEXT: csel w0, w0, w1, mi
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_or_one_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp one double %v0, %v1
|
|
%c1 = fcmp olt double %v2, %v3
|
|
%cr = or i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: select_or_olt_ueq:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d2, d3, #4, pl
|
|
; CHECK-NEXT: fccmp d2, d3, #1, ne
|
|
; CHECK-NEXT: csel w0, w0, w1, vs
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_or_olt_ueq(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp olt double %v0, %v1
|
|
%c1 = fcmp ueq double %v2, %v3
|
|
%cr = or i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: select_or_ueq_olt:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d0, d1, #8, le
|
|
; CHECK-NEXT: fccmp d2, d3, #8, mi
|
|
; CHECK-NEXT: csel w0, w0, w1, mi
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_or_ueq_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp ueq double %v0, %v1
|
|
%c1 = fcmp olt double %v2, %v3
|
|
%cr = or i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: select_or_olt_ogt_ueq:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d2, d3, #0, pl
|
|
; CHECK-NEXT: fccmp d4, d5, #4, le
|
|
; CHECK-NEXT: fccmp d4, d5, #1, ne
|
|
; CHECK-NEXT: csel w0, w0, w1, vs
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_or_olt_ogt_ueq(double %v0, double %v1, double %v2, double %v3, double %v4, double %v5, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp olt double %v0, %v1
|
|
%c1 = fcmp ogt double %v2, %v3
|
|
%c2 = fcmp ueq double %v4, %v5
|
|
%c3 = or i1 %c1, %c0
|
|
%cr = or i1 %c2, %c3
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: select_or_olt_ueq_ogt:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-NEXT: fcmp d0, d1
|
|
; CHECK-NEXT: fccmp d2, d3, #4, pl
|
|
; CHECK-NEXT: fccmp d2, d3, #1, ne
|
|
; CHECK-NEXT: fccmp d4, d5, #0, vc
|
|
; CHECK-NEXT: csel w0, w0, w1, gt
|
|
; CHECK-NEXT: ret
|
|
define i32 @select_or_olt_ueq_ogt(double %v0, double %v1, double %v2, double %v3, double %v4, double %v5, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp olt double %v0, %v1
|
|
%c1 = fcmp ueq double %v2, %v3
|
|
%c2 = fcmp ogt double %v4, %v5
|
|
%c3 = or i1 %c1, %c0
|
|
%cr = or i1 %c2, %c3
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; Verify that we correctly promote f16.
|
|
|
|
; CHECK-LABEL: half_select_and_olt_oge:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0
|
|
; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1
|
|
; CHECK-NEXT: fcmp [[S0]], [[S1]]
|
|
; CHECK-DAG: fcvt [[S2:s[0-9]+]], h2
|
|
; CHECK-DAG: fcvt [[S3:s[0-9]+]], h3
|
|
; CHECK-NEXT: fccmp [[S2]], [[S3]], #8, mi
|
|
; CHECK-NEXT: csel w0, w0, w1, ge
|
|
; CHECK-NEXT: ret
|
|
define i32 @half_select_and_olt_oge(half %v0, half %v1, half %v2, half %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp olt half %v0, %v1
|
|
%c1 = fcmp oge half %v2, %v3
|
|
%cr = and i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; CHECK-LABEL: half_select_and_olt_one:
|
|
; CHECK-LABEL: ; BB#0:
|
|
; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0
|
|
; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1
|
|
; CHECK-NEXT: fcmp [[S0]], [[S1]]
|
|
; CHECK-DAG: fcvt [[S2:s[0-9]+]], h2
|
|
; CHECK-DAG: fcvt [[S3:s[0-9]+]], h3
|
|
; CHECK-NEXT: fccmp [[S2]], [[S3]], #4, mi
|
|
; CHECK-NEXT: fccmp [[S2]], [[S3]], #1, ne
|
|
; CHECK-NEXT: csel w0, w0, w1, vc
|
|
; CHECK-NEXT: ret
|
|
define i32 @half_select_and_olt_one(half %v0, half %v1, half %v2, half %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp olt half %v0, %v1
|
|
%c1 = fcmp one half %v2, %v3
|
|
%cr = and i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
; Also verify that we don't try to generate f128 FCCMPs, using RT calls instead.
|
|
|
|
; CHECK-LABEL: f128_select_and_olt_oge:
|
|
; CHECK: bl ___lttf2
|
|
; CHECK: bl ___getf2
|
|
define i32 @f128_select_and_olt_oge(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32 %b) #0 {
|
|
%c0 = fcmp olt fp128 %v0, %v1
|
|
%c1 = fcmp oge fp128 %v2, %v3
|
|
%cr = and i1 %c1, %c0
|
|
%sel = select i1 %cr, i32 %a, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|