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6c7f917b92
e.g Currently we'll generate following instructions if the immediate is too wide:
MOV X0, WideImmediate
ADD X1, BaseReg, X0
LDR X2, [X1, 0]
Using [Base+XReg] addressing mode can save one ADD as following:
MOV X0, WideImmediate
LDR X2, [BaseReg, X0]
Differential Revision: http://reviews.llvm.org/D5477
llvm-svn: 219665
32 lines
905 B
LLVM
32 lines
905 B
LLVM
; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
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; Can't fold the increment by 1<<12 into a post-increment load
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; rdar://10301335
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@test_data = common global i32 0, align 4
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define void @t() nounwind ssp {
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; CHECK-LABEL: t:
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entry:
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br label %for.body
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for.body:
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; CHECK: for.body
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; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}, x{{[0-9]+}}]
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; CHECK: add x[[REG:[0-9]+]],
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; CHECK: x[[REG]], #1, lsl #12
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%0 = shl nsw i64 %indvars.iv, 12
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%add = add nsw i64 %0, 34628173824
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%1 = inttoptr i64 %add to i32*
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%2 = load volatile i32* %1, align 4096
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store volatile i32 %2, i32* @test_data, align 4
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%indvars.iv.next = add i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, 200
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret void
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}
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