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dc5e1808f1
While fixing up the register classes in the machine combiner in a previous commit I missed one. This fixes the last one and adds a test case. llvm-svn: 221308
38 lines
1.0 KiB
LLVM
38 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s | FileCheck %s
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; Test that we use the correct register class.
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define i32 @mul_add_imm(i32 %a, i32 %b) {
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; CHECK-LABEL: mul_add_imm
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; CHECK: orr [[REG:w[0-9]+]], wzr, #0x4
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; CHECK-NEXT: madd {{w[0-9]+}}, w0, w1, [[REG]]
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%1 = mul i32 %a, %b
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%2 = add i32 %1, 4
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ret i32 %2
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}
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define i32 @mul_sub_imm1(i32 %a, i32 %b) {
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; CHECK-LABEL: mul_sub_imm1
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; CHECK: orr [[REG:w[0-9]+]], wzr, #0x4
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; CHECK-NEXT: msub {{w[0-9]+}}, w0, w1, [[REG]]
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%1 = mul i32 %a, %b
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%2 = sub i32 4, %1
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ret i32 %2
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}
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; bugpoint reduced test case. This only tests that we pass the MI verifier.
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define void @mul_add_imm2() {
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entry:
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br label %for.body
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for.body:
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br i1 undef, label %for.body, label %for.body8
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for.body8:
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%0 = mul i64 undef, -3
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%mul1971 = add i64 %0, -3
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%cmp7 = icmp slt i64 %mul1971, 1390451930000
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br i1 %cmp7, label %for.body8, label %for.end20
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for.end20:
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ret void
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}
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