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0d99339102
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
209 lines
5.2 KiB
LLVM
209 lines
5.2 KiB
LLVM
; Test 64-bit signed division and remainder when the divisor is
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; a signed-extended i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i64 @foo()
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; Test register division. The result is in the second of the two registers.
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define void @f1(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgfr %r2, %r4
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; CHECK: stg %r3, 0(%r5)
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; CHECK: br %r14
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%bext = sext i32 %b to i64
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%div = sdiv i64 %a, %bext
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store i64 %div, i64 *%dest
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ret void
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}
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; Test register remainder. The result is in the first of the two registers.
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define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgfr %r2, %r4
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; CHECK: stg %r2, 0(%r5)
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; CHECK: br %r14
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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store i64 %rem, i64 *%dest
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ret void
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}
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; Test that division and remainder use a single instruction.
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define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgfr %r2, %r4
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; CHECK: ogr %r2, %r3
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; CHECK: br %r14
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%bext = sext i32 %b to i64
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%div = sdiv i64 %a, %bext
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%rem = srem i64 %a, %bext
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%or = or i64 %rem, %div
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ret i64 %or
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}
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; Test register division when the dividend is zero rather than sign extended.
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; We can't use dsgfr here
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define void @f4(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: dsgfr
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%div = sdiv i64 %a, %bext
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store i64 %div, i64 *%dest
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ret void
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}
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; ...likewise remainder.
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define void @f5(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: dsgfr
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; CHECK: br %r14
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%bext = zext i32 %b to i64
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%rem = srem i64 %a, %bext
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store i64 %rem, i64 *%dest
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ret void
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}
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; Test memory division with no displacement.
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define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: stg %r3, 0(%r5)
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; CHECK: br %r14
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%b = load i32 *%src
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%bext = sext i32 %b to i64
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%div = sdiv i64 %a, %bext
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store i64 %div, i64 *%dest
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ret void
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}
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; Test memory remainder with no displacement.
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define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: stg %r2, 0(%r5)
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; CHECK: br %r14
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%b = load i32 *%src
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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store i64 %rem, i64 *%dest
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ret void
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}
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; Test both memory division and memory remainder.
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define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: {{%r[234]}}
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK-NOT: {{dsgf|dsgfr}}
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; CHECK: ogr %r2, %r3
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; CHECK: br %r14
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%b = load i32 *%src
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%bext = sext i32 %b to i64
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%div = sdiv i64 %a, %bext
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%rem = srem i64 %a, %bext
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%or = or i64 %rem, %div
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ret i64 %or
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}
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; Check the high end of the DSGF range.
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define i64 @f9(i64 %dummy, i64 %a, i32 *%src) {
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; CHECK-LABEL: f9:
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; CHECK: dsgf %r2, 524284(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%b = load i32 *%ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f10(i64 %dummy, i64 %a, i32 *%src) {
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; CHECK-LABEL: f10:
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; CHECK: agfi %r4, 524288
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%b = load i32 *%ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check the high end of the negative aligned DSGF range.
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define i64 @f11(i64 %dummy, i64 %a, i32 *%src) {
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; CHECK-LABEL: f11:
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; CHECK: dsgf %r2, -4(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -1
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%b = load i32 *%ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check the low end of the DSGF range.
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define i64 @f12(i64 %dummy, i64 %a, i32 *%src) {
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; CHECK-LABEL: f12:
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; CHECK: dsgf %r2, -524288(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131072
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%b = load i32 *%ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f13(i64 %dummy, i64 %a, i32 *%src) {
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; CHECK-LABEL: f13:
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; CHECK: agfi %r4, -524292
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; CHECK: dsgf %r2, 0(%r4)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 -131073
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%b = load i32 *%ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Check that DSGF allows an index.
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define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f14:
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; CHECK: dsgf %r2, 524287(%r5,%r4)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 *%ptr
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%bext = sext i32 %b to i64
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%rem = srem i64 %a, %bext
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ret i64 %rem
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}
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; Make sure that we still use DSGFR rather than DSGR in cases where
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; a load and division cannot be combined.
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define void @f15(i64 *%dest, i32 *%src) {
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; CHECK-LABEL: f15:
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; CHECK: l [[B:%r[0-9]+]], 0(%r3)
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; CHECK: brasl %r14, foo@PLT
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; CHECK: lgr %r1, %r2
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; CHECK: dsgfr %r0, [[B]]
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; CHECK: br %r14
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%b = load i32 *%src
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%a = call i64 @foo()
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%ext = sext i32 %b to i64
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%div = sdiv i64 %a, %ext
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store i64 %div, i64 *%dest
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ret void
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}
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