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6956c38e1a
We recently discovered an issue that reinforces what a good idea it is to always specify -mcpu in our code generation tests, particularly for -mattr=+vsx. This patch ensures that all tests that specify -mattr=+vsx also specify -mcpu=pwr7 or -mcpu=pwr8, as appropriate. Some of the uses of -mattr=+vsx added recently don't make much sense (when specified for -mtriple=powerpc-apple-darwin8 or -march=ppc32, for example). For cases like this I've just removed the extra VSX test commands; there's enough coverage without them. llvm-svn: 220173
25 lines
1.2 KiB
LLVM
25 lines
1.2 KiB
LLVM
; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
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define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
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%tmp = load <4 x float>* %P3 ; <<4 x float>> [#uses=1]
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%tmp3 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1]
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%tmp4 = fmul <4 x float> %tmp, %tmp3 ; <<4 x float>> [#uses=1]
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store <4 x float> %tmp4, <4 x float>* %P3
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store <4 x float> zeroinitializer, <4 x float>* %P1
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store <4 x i32> zeroinitializer, <4 x i32>* %P2
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ret void
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}
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; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
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; to vmaddfp (so it would IEEE compliant with zero sign propagation).
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; CHECK: @VXOR
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; CHECK: vsplti
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; CHECK: vxor
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define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) {
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store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), <4 x i32>* %P2
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store <8 x i16> < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >, <8 x i16>* %P3
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ret void
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}
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; CHECK: @VSPLTI
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; CHECK: vsplti
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