mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 11:42:57 +01:00
261 lines
8.5 KiB
LLVM
261 lines
8.5 KiB
LLVM
; RUN: llc -march=mipsel < %s | FileCheck %s
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@x = common global i32 0, align 4
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define i32 @AtomicLoadAdd32(i32 %incr) nounwind {
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entry:
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%0 = atomicrmw add i32* @x, i32 %incr monotonic
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ret i32 %0
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; CHECK: AtomicLoadAdd32:
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; CHECK: lw $[[R0:[0-9]+]], %got(x)
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
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; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4
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; CHECK: sc $[[R2]], 0($[[R0]])
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; CHECK: beq $[[R2]], $zero, $[[BB0]]
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}
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define i32 @AtomicLoadNand32(i32 %incr) nounwind {
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entry:
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%0 = atomicrmw nand i32* @x, i32 %incr monotonic
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ret i32 %0
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; CHECK: AtomicLoadNand32:
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; CHECK: lw $[[R0:[0-9]+]], %got(x)
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
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; CHECK: and $[[R3:[0-9]+]], $[[R1]], $4
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; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R3]]
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; CHECK: sc $[[R2]], 0($[[R0]])
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; CHECK: beq $[[R2]], $zero, $[[BB0]]
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}
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define i32 @AtomicSwap32(i32 %newval) nounwind {
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entry:
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%newval.addr = alloca i32, align 4
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store i32 %newval, i32* %newval.addr, align 4
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%tmp = load i32* %newval.addr, align 4
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%0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
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ret i32 %0
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; CHECK: AtomicSwap32:
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; CHECK: lw $[[R0:[0-9]+]], %got(x)
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll ${{[0-9]+}}, 0($[[R0]])
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; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]])
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; CHECK: beq $[[R2]], $zero, $[[BB0]]
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}
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define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
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entry:
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%newval.addr = alloca i32, align 4
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store i32 %newval, i32* %newval.addr, align 4
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%tmp = load i32* %newval.addr, align 4
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%0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic
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ret i32 %0
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; CHECK: AtomicCmpSwap32:
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; CHECK: lw $[[R0:[0-9]+]], %got(x)
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $2, 0($[[R0]])
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; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
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; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]])
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; CHECK: beq $[[R2]], $zero, $[[BB0]]
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; CHECK: $[[BB1]]:
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}
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@y = common global i8 0, align 1
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define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
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entry:
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%0 = atomicrmw add i8* @y, i8 %incr monotonic
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ret i8 %0
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; CHECK: AtomicLoadAdd8:
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; CHECK: lw $[[R0:[0-9]+]], %got(y)
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; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
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; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
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; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
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; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
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; CHECK: ori $[[R5:[0-9]+]], $zero, 255
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; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
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; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
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; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
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; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
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; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
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; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
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; CHECK: sc $[[R14]], 0($[[R2]])
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; CHECK: beq $[[R14]], $zero, $[[BB0]]
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; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
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; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
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; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
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; CHECK: sra $2, $[[R17]], 24
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}
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define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
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entry:
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%0 = atomicrmw sub i8* @y, i8 %incr monotonic
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ret i8 %0
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; CHECK: AtomicLoadSub8:
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; CHECK: lw $[[R0:[0-9]+]], %got(y)
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; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
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; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
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; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
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; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
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; CHECK: ori $[[R5:[0-9]+]], $zero, 255
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; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
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; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
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; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
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; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
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; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
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; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
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; CHECK: sc $[[R14]], 0($[[R2]])
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; CHECK: beq $[[R14]], $zero, $[[BB0]]
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; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
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; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
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; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
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; CHECK: sra $2, $[[R17]], 24
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}
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define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
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entry:
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%0 = atomicrmw nand i8* @y, i8 %incr monotonic
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ret i8 %0
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; CHECK: AtomicLoadNand8:
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; CHECK: lw $[[R0:[0-9]+]], %got(y)
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; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
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; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
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; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
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; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
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; CHECK: ori $[[R5:[0-9]+]], $zero, 255
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; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
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; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
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; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
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; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
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; CHECK: nor $[[R11:[0-9]+]], $zero, $[[R18]]
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; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
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; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
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; CHECK: sc $[[R14]], 0($[[R2]])
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; CHECK: beq $[[R14]], $zero, $[[BB0]]
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; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
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; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
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; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
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; CHECK: sra $2, $[[R17]], 24
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}
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define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
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entry:
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%0 = atomicrmw xchg i8* @y, i8 %newval monotonic
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ret i8 %0
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; CHECK: AtomicSwap8:
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; CHECK: lw $[[R0:[0-9]+]], %got(y)
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; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
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; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
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; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
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; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
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; CHECK: ori $[[R5:[0-9]+]], $zero, 255
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; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
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; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
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; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
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; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
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; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R9]]
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; CHECK: sc $[[R14]], 0($[[R2]])
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; CHECK: beq $[[R14]], $zero, $[[BB0]]
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; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
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; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
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; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
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; CHECK: sra $2, $[[R17]], 24
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}
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define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
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entry:
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%0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic
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ret i8 %0
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; CHECK: AtomicCmpSwap8:
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; CHECK: lw $[[R0:[0-9]+]], %got(y)
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; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
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; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
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; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
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; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
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; CHECK: ori $[[R5:[0-9]+]], $zero, 255
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; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
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; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
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; CHECK: andi $[[R8:[0-9]+]], $4, 255
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; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
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; CHECK: andi $[[R10:[0-9]+]], $5, 255
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; CHECK: sllv $[[R11:[0-9]+]], $[[R10]], $[[R4]]
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; CHECK: $[[BB0:[A-Z_0-9]+]]:
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; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]])
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; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]
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; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
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; CHECK: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
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; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
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; CHECK: sc $[[R15]], 0($[[R2]])
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; CHECK: beq $[[R15]], $zero, $[[BB0]]
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; CHECK: $[[BB1]]:
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; CHECK: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
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; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
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; CHECK: sra $2, $[[R17]], 24
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}
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@countsint = common global i32 0, align 4
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define i32 @CheckSync(i32 %v) nounwind noinline {
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entry:
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%0 = atomicrmw add i32* @countsint, i32 %v seq_cst
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ret i32 %0
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; CHECK: CheckSync:
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; CHECK: sync 0
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; CHECK: ll
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; CHECK: sc
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; CHECK: beq
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; CHECK: sync 0
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}
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; make sure that this assertion in
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; TwoAddressInstructionPass::TryInstructionTransform does not fail:
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;
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; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) &&
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;
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; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an
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; operand of an atomic instruction with register $zero.
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@a = external global i32
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define i32 @zeroreg() nounwind {
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entry:
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%0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst
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%1 = icmp eq i32 %0, 1
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%conv = zext i1 %1 to i32
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ret i32 %conv
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}
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