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llvm-mirror/test/MC/Mips/mips-coprocessor-encodings.s
David Chisnall 41ea5b7975 Expose move to/from coprocessor instructions in MIPS64 mode.
Note: [D]M{T,F}CP2 is just a recommended encoding.  Vendors often provide a
custom CP2 that interprets instructions differently and may wish to add their
own instructions that use this opcode.  We should ensure that this is easy to
do.  I will probably add a 'has custom CP{0-3}' subtarget flag to make this
easy: We want to avoid the GCC situation where every MIPS vendor makes a custom
fork that breaks every other MIPS CPU and so can't be merged upstream.

llvm-svn: 165711
2012-10-11 10:21:34 +00:00

38 lines
1.5 KiB
ArmAsm

# RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding | FileCheck --check-prefix=MIPS64 %s
# MIPS64: dmtc0 $12, $16, 2 # encoding: [0x40,0xac,0x80,0x02]
# MIPS64: dmtc0 $12, $16, 0 # encoding: [0x40,0xac,0x80,0x00]
# MIPS64: mtc0 $12, $16, 2 # encoding: [0x40,0x8c,0x80,0x02]
# MIPS64: mtc0 $12, $16, 0 # encoding: [0x40,0x8c,0x80,0x00]
# MIPS64: dmfc0 $12, $16, 2 # encoding: [0x40,0x2c,0x80,0x02]
# MIPS64: dmfc0 $12, $16, 0 # encoding: [0x40,0x2c,0x80,0x00]
# MIPS64: mfc0 $12, $16, 2 # encoding: [0x40,0x0c,0x80,0x02]
# MIPS64: mfc0 $12, $16, 0 # encoding: [0x40,0x0c,0x80,0x00]
dmtc0 $12, $16, 2
dmtc0 $12, $16
mtc0 $12, $16, 2
mtc0 $12, $16
dmfc0 $12, $16, 2
dmfc0 $12, $16
mfc0 $12, $16, 2
mfc0 $12, $16
# MIPS64: dmtc2 $12, $16, 2 # encoding: [0x48,0xac,0x80,0x02]
# MIPS64: dmtc2 $12, $16, 0 # encoding: [0x48,0xac,0x80,0x00]
# MIPS64: mtc2 $12, $16, 2 # encoding: [0x48,0x8c,0x80,0x02]
# MIPS64: mtc2 $12, $16, 0 # encoding: [0x48,0x8c,0x80,0x00]
# MIPS64: dmfc2 $12, $16, 2 # encoding: [0x48,0x2c,0x80,0x02]
# MIPS64: dmfc2 $12, $16, 0 # encoding: [0x48,0x2c,0x80,0x00]
# MIPS64: mfc2 $12, $16, 2 # encoding: [0x48,0x0c,0x80,0x02]
# MIPS64: mfc2 $12, $16, 0 # encoding: [0x48,0x0c,0x80,0x00]
dmtc2 $12, $16, 2
dmtc2 $12, $16
mtc2 $12, $16, 2
mtc2 $12, $16
dmfc2 $12, $16, 2
dmfc2 $12, $16
mfc2 $12, $16, 2
mfc2 $12, $16