1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/lib/Target
Misha Brukman 0fae161230 The actual order of parameters in a 2-reg-immediate assembly instructions is
"rs1, imm, rd": most importantly, rd goes last.

llvm-svn: 6456
2003-05-31 04:22:26 +00:00
..
Sparc The actual order of parameters in a 2-reg-immediate assembly instructions is 2003-05-31 04:22:26 +00:00
X86 Renamed opIsDef to opIsDefOnly. 2003-05-27 00:03:17 +00:00
Makefile X86 target builds fine now 2002-11-20 20:17:03 +00:00
MRegisterInfo.cpp Capture more information in ctor 2002-12-28 20:34:18 +00:00
Target.td Added the target-independent part of TableGen data. 2003-05-29 18:48:17 +00:00
TargetData.cpp * Fix divide by zero error with empty structs 2003-05-21 18:08:44 +00:00
TargetInstrInfo.cpp Rename MachineInstrInfo -> TargetInstrInfo 2003-01-14 22:00:31 +00:00
TargetMachine.cpp The promotion rules are the same for all targets, they are set by the C standard. 2003-04-26 19:47:36 +00:00
TargetSchedInfo.cpp More renamings of Target/Machine*Info to Target/Target*Info 2002-12-29 03:13:05 +00:00