Petar Avramovic 0fbf8111e0 [AMDGPU][MC] Add tfe disassembler support MIMG opcodes ... With tfe on there can be a vgpr write to vdata+1. Add tablegen support for 5 register vdata store. This is required for 4 register vdata store with tfe. Differential Revision: https://reviews.llvm.org/D94960		2021-01-20 10:37:09 +01:00
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AArch64	[ARM] Update existing test case with +pauth targets	2021-01-11 15:39:13 +00:00
AMDGPU	[AMDGPU][MC] Add tfe disassembler support MIMG opcodes	2021-01-20 10:37:09 +01:00
ARC
ARM
Hexagon
Lanai
Mips
MSP430
PowerPC	[PowerPC] Only use some extend mne if assembler is modern enough	2021-01-14 20:36:10 +00:00
RISCV
Sparc
SystemZ
WebAssembly	[WebAssembly] Remove exnref and br_on_exn	2021-01-09 02:02:54 -08:00
X86	[X86] Add TLBSYNC, INVLPGB and SNP instructions	2021-01-08 22:28:53 +05:30
XCore