mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 04:32:44 +01:00
b87a61b44f
This matches the ARM behavior. In both cases, the register is part of the optional Performance Monitors extension, so, add the feature, and enable it for the A-class processors we support. Differential Revision: http://reviews.llvm.org/D12425 llvm-svn: 246555
16 lines
578 B
LLVM
16 lines
578 B
LLVM
; RUN: llc -mtriple=aarch64-unknown-unknown -asm-verbose=false < %s |\
|
|
; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=PERFMON
|
|
; RUN: llc -mtriple=aarch64-unknown-unknown -mattr=-perfmon -asm-verbose=false < %s |\
|
|
; RUN: FileCheck %s --check-prefix=CHECK --check-prefix=NOPERFMON
|
|
|
|
define i64 @test_readcyclecounter() nounwind {
|
|
; CHECK-LABEL: test_readcyclecounter:
|
|
; PERFMON-NEXT: mrs x0, PMCCNTR_EL0
|
|
; NOPERFMON-NEXT: mov x0, xzr
|
|
; CHECK-NEXT: ret
|
|
%tmp0 = call i64 @llvm.readcyclecounter()
|
|
ret i64 %tmp0
|
|
}
|
|
|
|
declare i64 @llvm.readcyclecounter()
|