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https://github.com/RPCS3/llvm-mirror.git
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ff0c489bc6
These instructions have been around for a long time, but we haven't supported intrinsics for them. The "new" versions use the CSx register for the start of the buffer instead of the K field in the Mx register. We need to use pseudo instructions for these instructions until after register allocation. The problem is that these instructions allocate a M0/CS0 or M1/CS1 pair. But, we can't generate code for the CSx set-up until after register allocation when the Mx register has been fixed for the instruction. There is a related clang patch. Patch by Brendon Cahoon. llvm-svn: 328724
295 lines
9.4 KiB
LLVM
295 lines
9.4 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK: m[[REG1:([0-1])]] = r0
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; CHECK: cs[[REG1]] = r1
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; CHECK: = memub(r1++#4:circ(m[[REG1]])
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define zeroext i8 @test1(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrub.pci(i8* %start, i32 4, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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%conv = trunc i32 %1 to i8
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ret i8 %conv
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadrub.pci(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test2
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; CHECK: m[[REG2:([0-1])]] = r0
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; CHECK: cs[[REG2]] = r1
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; CHECK: = memb(r1++#4:circ(m[[REG2]])
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define zeroext i8 @test2(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrb.pci(i8* %start, i32 4, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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%conv = trunc i32 %1 to i8
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ret i8 %conv
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadrb.pci(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test3
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; CHECK: m[[REG3:([0-1])]] = r0
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; CHECK: cs[[REG3]] = r1
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; CHECK: = memuh(r1++#4:circ(m[[REG3]])
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define zeroext i16 @test3(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadruh.pci(i8* %start, i32 4, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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%conv = trunc i32 %1 to i16
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ret i16 %conv
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadruh.pci(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test4
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; CHECK: m[[REG4:([0-1])]] = r0
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; CHECK: cs[[REG4]] = r1
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; CHECK: = memh(r1++#4:circ(m[[REG4]])
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define signext i16 @test4(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrh.pci(i8* %start, i32 4, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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%conv = trunc i32 %1 to i16
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ret i16 %conv
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadrh.pci(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test5
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; CHECK: m[[REG5:([0-1])]] = r0
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; CHECK: cs[[REG5]] = r1
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; CHECK: = memw(r1++#4:circ(m[[REG5]])
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define i32 @test5(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadri.pci(i8* %start, i32 4, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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ret i32 %1
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadri.pci(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test6
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; CHECK: m[[REG6:([0-1])]] = r0
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; CHECK: cs[[REG6]] = r1
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; CHECK: = memd(r1++#8:circ(m[[REG6]])
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define i64 @test6(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i64, i8* } @llvm.hexagon.L2.loadrd.pci(i8* %start, i32 8, i32 %mod, i8* %start)
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%1 = extractvalue { i64, i8* } %0, 0
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ret i64 %1
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}
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declare { i64, i8* } @llvm.hexagon.L2.loadrd.pci(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test7
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; CHECK: m[[REG7:([0-1])]] = r0
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; CHECK: cs[[REG7]] = r1
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; CHECK: = memub(r1++I:circ(m[[REG7]])
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define zeroext i8 @test7(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrub.pcr(i8* %start, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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%conv = trunc i32 %1 to i8
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ret i8 %conv
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadrub.pcr(i8*, i32, i8* nocapture) #1
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; CHECK-LABEL: test8
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; CHECK: m[[REG8:([0-1])]] = r0
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; CHECK: cs[[REG8]] = r1
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; CHECK: = memb(r1++I:circ(m[[REG8]])
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define zeroext i8 @test8(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrb.pcr(i8* %start, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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%conv = trunc i32 %1 to i8
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ret i8 %conv
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadrb.pcr(i8*, i32, i8* nocapture) #1
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; CHECK-LABEL: test9
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; CHECK: m[[REG9:([0-1])]] = r0
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; CHECK: cs[[REG9]] = r1
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; CHECK: = memuh(r1++I:circ(m[[REG9]])
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define zeroext i16 @test9(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadruh.pcr(i8* %start, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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%conv = trunc i32 %1 to i16
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ret i16 %conv
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadruh.pcr(i8*, i32, i8* nocapture) #1
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; CHECK-LABEL: test10
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; CHECK: m[[REG10:([0-1])]] = r0
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; CHECK: cs[[REG10]] = r1
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; CHECK: = memh(r1++I:circ(m[[REG10]])
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define signext i16 @test10(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadrh.pcr(i8* %start, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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%conv = trunc i32 %1 to i16
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ret i16 %conv
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadrh.pcr(i8*, i32, i8* nocapture) #1
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; CHECK-LABEL: test11
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; CHECK: m[[REG11:([0-1])]] = r0
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; CHECK: cs[[REG11]] = r1
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; CHECK: = memw(r1++I:circ(m[[REG11]])
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define i32 @test11(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i32, i8* } @llvm.hexagon.L2.loadri.pcr(i8* %start, i32 %mod, i8* %start)
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%1 = extractvalue { i32, i8* } %0, 0
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ret i32 %1
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}
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declare { i32, i8* } @llvm.hexagon.L2.loadri.pcr(i8*, i32, i8* nocapture) #1
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; CHECK-LABEL: test12
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; CHECK: m[[REG12:([0-1])]] = r0
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; CHECK: cs[[REG12]] = r1
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; CHECK: = memd(r1++I:circ(m[[REG12]])
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define i64 @test12(i32 %mod, i8* %start) local_unnamed_addr #0 {
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entry:
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%0 = tail call { i64, i8* } @llvm.hexagon.L2.loadrd.pcr(i8* %start, i32 %mod, i8* %start)
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%1 = extractvalue { i64, i8* } %0, 0
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ret i64 %1
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}
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declare { i64, i8* } @llvm.hexagon.L2.loadrd.pcr(i8*, i32, i8* nocapture) #1
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; CHECK-LABEL: test13
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; CHECK: m[[REG13:([0-1])]] = r0
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; CHECK: cs[[REG13]] = r1
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; CHECK: memb(r1++#4:circ(m[[REG13]])) =
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define void @test13(i32 %mod, i8* %start, i8 zeroext %v) local_unnamed_addr #0 {
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entry:
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%conv = zext i8 %v to i32
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%0 = tail call i8* @llvm.hexagon.S2.storerb.pci(i8* %start, i32 4, i32 %mod, i32 %conv, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storerb.pci(i8*, i32, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test14
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; CHECK: m[[REG14:([0-1])]] = r0
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; CHECK: cs[[REG14]] = r1
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; CHECK: memh(r1++#4:circ(m[[REG14]])) =
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define void @test14(i32 %mod, i8* %start, i16 signext %v) local_unnamed_addr #0 {
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entry:
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%conv = sext i16 %v to i32
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%0 = tail call i8* @llvm.hexagon.S2.storerh.pci(i8* %start, i32 4, i32 %mod, i32 %conv, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storerh.pci(i8*, i32, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test15
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; CHECK: m[[REG15:([0-1])]] = r0
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; CHECK: cs[[REG15]] = r1
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; CHECK: memh(r1++#4:circ(m[[REG15]])) = r{{[0-9]+}}.h
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define void @test15(i32 %mod, i8* %start, i16 signext %v) local_unnamed_addr #0 {
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entry:
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%conv = sext i16 %v to i32
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%0 = tail call i8* @llvm.hexagon.S2.storerf.pci(i8* %start, i32 4, i32 %mod, i32 %conv, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storerf.pci(i8*, i32, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test16
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; CHECK: m[[REG16:([0-1])]] = r0
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; CHECK: cs[[REG16]] = r1
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; CHECK: memw(r1++#4:circ(m[[REG16]])) =
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define void @test16(i32 %mod, i8* %start, i32 %v) local_unnamed_addr #0 {
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entry:
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%0 = tail call i8* @llvm.hexagon.S2.storeri.pci(i8* %start, i32 4, i32 %mod, i32 %v, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storeri.pci(i8*, i32, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test17
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; CHECK: m[[REG17:([0-1])]] = r0
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; CHECK: cs[[REG17]] = r1
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; CHECK: memd(r1++#8:circ(m[[REG17]])) =
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define void @test17(i32 %mod, i8* %start, i64 %v) local_unnamed_addr #0 {
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entry:
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%0 = tail call i8* @llvm.hexagon.S2.storerd.pci(i8* %start, i32 8, i32 %mod, i64 %v, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storerd.pci(i8*, i32, i32, i64, i8* nocapture) #1
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; CHECK-LABEL: test18
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; CHECK: m[[REG18:([0-1])]] = r0
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; CHECK: cs[[REG18]] = r1
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; CHECK: memb(r1++I:circ(m[[REG18]])) =
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define void @test18(i32 %mod, i8* %start, i8 zeroext %v) local_unnamed_addr #0 {
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entry:
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%conv = zext i8 %v to i32
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%0 = tail call i8* @llvm.hexagon.S2.storerb.pcr(i8* %start, i32 %mod, i32 %conv, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storerb.pcr(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test19
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; CHECK: m[[REG19:([0-1])]] = r0
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; CHECK: cs[[REG19]] = r1
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; CHECK: memh(r1++I:circ(m[[REG19]])) =
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define void @test19(i32 %mod, i8* %start, i16 signext %v) local_unnamed_addr #0 {
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entry:
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%conv = sext i16 %v to i32
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%0 = tail call i8* @llvm.hexagon.S2.storerh.pcr(i8* %start, i32 %mod, i32 %conv, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storerh.pcr(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test20
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; CHECK: m[[REG20:([0-1])]] = r0
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; CHECK: cs[[REG20]] = r1
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; CHECK: memh(r1++I:circ(m[[REG20]])) = r{{[0-9]+}}.h
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define void @test20(i32 %mod, i8* %start, i16 signext %v) local_unnamed_addr #0 {
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entry:
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%conv = sext i16 %v to i32
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%0 = tail call i8* @llvm.hexagon.S2.storerf.pcr(i8* %start, i32 %mod, i32 %conv, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storerf.pcr(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test21
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; CHECK: m[[REG21:([0-1])]] = r0
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; CHECK: cs[[REG21]] = r1
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; CHECK: memw(r1++I:circ(m[[REG21]])) =
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define void @test21(i32 %mod, i8* %start, i32 %v) local_unnamed_addr #0 {
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entry:
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%0 = tail call i8* @llvm.hexagon.S2.storeri.pcr(i8* %start, i32 %mod, i32 %v, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storeri.pcr(i8*, i32, i32, i8* nocapture) #1
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; CHECK-LABEL: test22
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; CHECK: m[[REG22:([0-1])]] = r0
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; CHECK: cs[[REG22]] = r1
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; CHECK: memd(r1++I:circ(m[[REG1]])) =
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define void @test22(i32 %mod, i8* %start, i64 %v) local_unnamed_addr #0 {
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entry:
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%0 = tail call i8* @llvm.hexagon.S2.storerd.pcr(i8* %start, i32 %mod, i64 %v, i8* %start)
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ret void
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}
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declare i8* @llvm.hexagon.S2.storerd.pcr(i8*, i32, i64, i8* nocapture) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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attributes #1 = { argmemonly nounwind }
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