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262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
70 lines
3.1 KiB
LLVM
70 lines
3.1 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: if (p{{[0-3]}}) v{{[0-9]+}} = v{{[0-9]+}}
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @fast9_detect_coarse(i8* nocapture readnone %img, i32 %xsize, i32 %stride, i32 %barrier, i32* nocapture %bitmask, i32 %boundary) #0 {
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entry:
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%0 = bitcast i32* %bitmask to <16 x i32>*
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%1 = mul i32 %boundary, -2
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%sub = add i32 %1, %xsize
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%rem = and i32 %boundary, 63
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%add = add i32 %sub, %rem
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%2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 -1)
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%3 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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%4 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %add)
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%5 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %3, <512 x i1> %4, i32 12)
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%and4 = and i32 %add, 511
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%cmp = icmp eq i32 %and4, 0
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%sMaskR.0 = select i1 %cmp, <16 x i32> %2, <16 x i32> %5
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%cmp547 = icmp sgt i32 %add, 0
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br i1 %cmp547, label %for.body.lr.ph, label %for.end
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for.body.lr.ph: ; preds = %entry
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%6 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %boundary)
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%7 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1> %6, i32 16843009)
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%8 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %7)
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%9 = add i32 %rem, %xsize
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%10 = add i32 %9, -1
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%11 = add i32 %10, %1
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%12 = lshr i32 %11, 9
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%13 = mul i32 %12, 16
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%14 = add nuw nsw i32 %13, 16
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%scevgep = getelementptr i32, i32* %bitmask, i32 %14
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br label %for.body
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for.body: ; preds = %for.body.lr.ph, %for.body
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%i.050 = phi i32 [ %add, %for.body.lr.ph ], [ %sub6, %for.body ]
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%sMask.049 = phi <16 x i32> [ %8, %for.body.lr.ph ], [ %2, %for.body ]
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%optr.048 = phi <16 x i32>* [ %0, %for.body.lr.ph ], [ %incdec.ptr, %for.body ]
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%15 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> undef, <16 x i32> %sMask.049)
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%incdec.ptr = getelementptr inbounds <16 x i32>, <16 x i32>* %optr.048, i32 1
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store <16 x i32> %15, <16 x i32>* %optr.048, align 64
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%sub6 = add nsw i32 %i.050, -512
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%cmp5 = icmp sgt i32 %sub6, 0
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br i1 %cmp5, label %for.body, label %for.cond.for.end_crit_edge
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for.cond.for.end_crit_edge: ; preds = %for.body
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%scevgep51 = bitcast i32* %scevgep to <16 x i32>*
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br label %for.end
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for.end: ; preds = %for.cond.for.end_crit_edge, %entry
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%optr.0.lcssa = phi <16 x i32>* [ %scevgep51, %for.cond.for.end_crit_edge ], [ %0, %entry ]
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%16 = load <16 x i32>, <16 x i32>* %optr.0.lcssa, align 64
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%17 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %16, <16 x i32> %sMaskR.0)
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store <16 x i32> %17, <16 x i32>* %optr.0.lcssa, align 64
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ret void
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}
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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declare <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1
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declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <512 x i1>, i32) #1
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declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1
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declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1
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declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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