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The architecture doesn't really have any native v4f32 operations except v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32 elements being used. Even so, using vector registers for <4 x float> and scalarising individual operations is much better than generating completely scalar code, since there's much less register pressure. It's also more efficient to do v4f32 comparisons by extending to 2 v2f64s, comparing those, then packing the result. This particularly helps with llvmpipe. Based on a patch by Richard Sandiford. llvm-svn: 236523
201 lines
7.0 KiB
LLVM
201 lines
7.0 KiB
LLVM
; Test vector merge high.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a canonical v16i8 merge high.
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define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vmrhb %v24, %v24, %v26
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 0, i32 16, i32 1, i32 17,
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i32 2, i32 18, i32 3, i32 19,
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i32 4, i32 20, i32 5, i32 21,
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i32 6, i32 22, i32 7, i32 23>
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ret <16 x i8> %ret
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}
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; Test a reversed v16i8 merge high.
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define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vmrhb %v24, %v26, %v24
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 16, i32 0, i32 17, i32 1,
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i32 18, i32 2, i32 19, i32 3,
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i32 20, i32 4, i32 21, i32 5,
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i32 22, i32 6, i32 23, i32 7>
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ret <16 x i8> %ret
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}
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; Test a v16i8 merge high with only the first operand being used.
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define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vmrhb %v24, %v24, %v24
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 0, i32 0, i32 1, i32 1,
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i32 2, i32 2, i32 3, i32 3,
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i32 4, i32 4, i32 5, i32 5,
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i32 6, i32 6, i32 7, i32 7>
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ret <16 x i8> %ret
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}
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; Test a v16i8 merge high with only the second operand being used.
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; This is converted into @f3 by target-independent code.
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define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vmrhb %v24, %v26, %v26
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 16, i32 16, i32 17, i32 17,
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i32 18, i32 18, i32 19, i32 19,
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i32 20, i32 20, i32 21, i32 21,
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i32 22, i32 22, i32 23, i32 23>
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ret <16 x i8> %ret
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}
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; Test a v16i8 merge with both operands being the same. This too is
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; converted into @f3 by target-independent code.
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define <16 x i8> @f5(<16 x i8> %val) {
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; CHECK-LABEL: f5:
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; CHECK: vmrhb %v24, %v24, %v24
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val, <16 x i8> %val,
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<16 x i32> <i32 0, i32 16, i32 17, i32 17,
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i32 18, i32 2, i32 3, i32 3,
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i32 20, i32 20, i32 5, i32 5,
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i32 6, i32 22, i32 23, i32 7>
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ret <16 x i8> %ret
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}
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; Test a v16i8 merge in which some of the indices are don't care.
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define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: vmrhb %v24, %v24, %v26
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 0, i32 undef, i32 1, i32 17,
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i32 undef, i32 18, i32 undef, i32 undef,
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i32 undef, i32 20, i32 5, i32 21,
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i32 undef, i32 22, i32 7, i32 undef>
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ret <16 x i8> %ret
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}
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; Test a v16i8 merge in which one of the operands is undefined and where
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; indices for that operand are "don't care". Target-independent code
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; converts the indices themselves into "undef"s.
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define <16 x i8> @f7(<16 x i8> %val) {
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; CHECK-LABEL: f7:
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; CHECK: vmrhb %v24, %v24, %v24
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> undef, <16 x i8> %val,
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<16 x i32> <i32 11, i32 16, i32 17, i32 5,
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i32 18, i32 10, i32 19, i32 19,
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i32 20, i32 20, i32 21, i32 3,
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i32 2, i32 22, i32 9, i32 23>
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ret <16 x i8> %ret
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}
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; Test a canonical v8i16 merge high.
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define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f8:
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; CHECK: vmrhh %v24, %v24, %v26
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; CHECK: br %r14
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%ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
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<8 x i32> <i32 0, i32 8, i32 1, i32 9,
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i32 2, i32 10, i32 3, i32 11>
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ret <8 x i16> %ret
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}
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; Test a reversed v8i16 merge high.
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define <8 x i16> @f9(<8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f9:
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; CHECK: vmrhh %v24, %v26, %v24
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; CHECK: br %r14
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%ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
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<8 x i32> <i32 8, i32 0, i32 9, i32 1,
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i32 10, i32 2, i32 11, i32 3>
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ret <8 x i16> %ret
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}
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; Test a canonical v4i32 merge high.
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define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f10:
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; CHECK: vmrhf %v24, %v24, %v26
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; CHECK: br %r14
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%ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> <i32 0, i32 4, i32 1, i32 5>
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ret <4 x i32> %ret
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}
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; Test a reversed v4i32 merge high.
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define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2) {
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; CHECK-LABEL: f11:
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; CHECK: vmrhf %v24, %v26, %v24
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; CHECK: br %r14
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%ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
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<4 x i32> <i32 4, i32 0, i32 5, i32 1>
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ret <4 x i32> %ret
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}
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; Test a canonical v2i64 merge high.
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define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f12:
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; CHECK: vmrhg %v24, %v24, %v26
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; CHECK: br %r14
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%ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
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<2 x i32> <i32 0, i32 2>
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ret <2 x i64> %ret
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}
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; Test a reversed v2i64 merge high.
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define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f13:
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; CHECK: vmrhg %v24, %v26, %v24
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; CHECK: br %r14
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%ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
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<2 x i32> <i32 2, i32 0>
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ret <2 x i64> %ret
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}
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; Test a canonical v4f32 merge high.
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define <4 x float> @f14(<4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f14:
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; CHECK: vmrhf %v24, %v24, %v26
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; CHECK: br %r14
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%ret = shufflevector <4 x float> %val1, <4 x float> %val2,
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<4 x i32> <i32 0, i32 4, i32 1, i32 5>
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ret <4 x float> %ret
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}
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; Test a reversed v4f32 merge high.
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define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f15:
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; CHECK: vmrhf %v24, %v26, %v24
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; CHECK: br %r14
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%ret = shufflevector <4 x float> %val1, <4 x float> %val2,
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<4 x i32> <i32 4, i32 0, i32 5, i32 1>
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ret <4 x float> %ret
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}
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; Test a canonical v2f64 merge high.
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define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2) {
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; CHECK-LABEL: f16:
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; CHECK: vmrhg %v24, %v24, %v26
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; CHECK: br %r14
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%ret = shufflevector <2 x double> %val1, <2 x double> %val2,
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<2 x i32> <i32 0, i32 2>
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ret <2 x double> %ret
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}
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; Test a reversed v2f64 merge high.
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define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2) {
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; CHECK-LABEL: f17:
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; CHECK: vmrhg %v24, %v26, %v24
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; CHECK: br %r14
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%ret = shufflevector <2 x double> %val1, <2 x double> %val2,
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<2 x i32> <i32 2, i32 0>
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ret <2 x double> %ret
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}
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