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31e1362588
TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
154 lines
3.5 KiB
LLVM
154 lines
3.5 KiB
LLVM
; RUN: llc < %s -march=sparcv9 -verify-machineinstrs | FileCheck %s
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; CHECK-LABEL: test_atomic_i32
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; CHECK: ld [%o0]
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; CHECK: membar
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; CHECK: ld [%o1]
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; CHECK: membar
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; CHECK: membar
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; CHECK: st {{.+}}, [%o2]
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define i32 @test_atomic_i32(i32* %ptr1, i32* %ptr2, i32* %ptr3) {
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entry:
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%0 = load atomic i32* %ptr1 acquire, align 8
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%1 = load atomic i32* %ptr2 acquire, align 8
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%2 = add i32 %0, %1
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store atomic i32 %2, i32* %ptr3 release, align 8
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ret i32 %2
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}
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; CHECK-LABEL: test_atomic_i64
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; CHECK: ldx [%o0]
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; CHECK: membar
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; CHECK: ldx [%o1]
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; CHECK: membar
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; CHECK: membar
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; CHECK: stx {{.+}}, [%o2]
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define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
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entry:
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%0 = load atomic i64* %ptr1 acquire, align 8
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%1 = load atomic i64* %ptr2 acquire, align 8
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%2 = add i64 %0, %1
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store atomic i64 %2, i64* %ptr3 release, align 8
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ret i64 %2
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}
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; CHECK-LABEL: test_cmpxchg_i32
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; CHECK: mov 123, [[R:%[gilo][0-7]]]
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; CHECK: cas [%o1], %o0, [[R]]
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define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
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entry:
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%b = cmpxchg i32* %ptr, i32 %a, i32 123 monotonic monotonic
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ret i32 %b
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}
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; CHECK-LABEL: test_cmpxchg_i64
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; CHECK: mov 123, [[R:%[gilo][0-7]]]
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; CHECK: casx [%o1], %o0, [[R]]
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define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
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entry:
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%b = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic monotonic
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ret i64 %b
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}
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; CHECK-LABEL: test_swap_i32
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; CHECK: mov 42, [[R:%[gilo][0-7]]]
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; CHECK: swap [%o1], [[R]]
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define i32 @test_swap_i32(i32 %a, i32* %ptr) {
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entry:
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%b = atomicrmw xchg i32* %ptr, i32 42 monotonic
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ret i32 %b
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}
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; CHECK-LABEL: test_swap_i64
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; CHECK: casx [%o1],
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define i64 @test_swap_i64(i64 %a, i64* %ptr) {
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entry:
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%b = atomicrmw xchg i64* %ptr, i64 42 monotonic
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ret i64 %b
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}
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; CHECK-LABEL: test_load_add_32
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; CHECK: membar
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; CHECK: add [[V:%[gilo][0-7]]], %o1, [[U:%[gilo][0-7]]]
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; CHECK: cas [%o0], [[V]], [[U]]
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; CHECK: membar
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define zeroext i32 @test_load_add_32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw add i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK-LABEL: test_load_sub_64
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; CHECK: membar
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; CHECK: sub
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; CHECK: casx [%o0]
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; CHECK: membar
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define zeroext i64 @test_load_sub_64(i64* %p, i64 zeroext %v) {
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entry:
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%0 = atomicrmw sub i64* %p, i64 %v seq_cst
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ret i64 %0
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}
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; CHECK-LABEL: test_load_xor_32
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; CHECK: membar
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; CHECK: xor
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; CHECK: cas [%o0]
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; CHECK: membar
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define zeroext i32 @test_load_xor_32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw xor i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK-LABEL: test_load_and_32
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; CHECK: membar
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; CHECK: and
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; CHECK-NOT: xor
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; CHECK: cas [%o0]
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; CHECK: membar
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define zeroext i32 @test_load_and_32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw and i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK-LABEL: test_load_nand_32
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; CHECK: membar
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; CHECK: and
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; CHECK: xor
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; CHECK: cas [%o0]
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; CHECK: membar
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define zeroext i32 @test_load_nand_32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw nand i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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; CHECK-LABEL: test_load_max_64
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; CHECK: membar
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; CHECK: cmp
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; CHECK: movg %xcc
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; CHECK: casx [%o0]
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; CHECK: membar
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define zeroext i64 @test_load_max_64(i64* %p, i64 zeroext %v) {
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entry:
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%0 = atomicrmw max i64* %p, i64 %v seq_cst
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ret i64 %0
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}
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; CHECK-LABEL: test_load_umin_32
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; CHECK: membar
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; CHECK: cmp
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; CHECK: movleu %icc
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; CHECK: cas [%o0]
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; CHECK: membar
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define zeroext i32 @test_load_umin_32(i32* %p, i32 zeroext %v) {
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entry:
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%0 = atomicrmw umin i32* %p, i32 %v seq_cst
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ret i32 %0
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}
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