Kevin Enderby b71a2e2f2e Update the X86 disassembler to use xacquire and xrelease when appropriate. ... This is a bit tricky as the xacquire and xrelease hints use the same bytes, 0xf2 and 0xf3, as the repne and rep prefixes. Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease and repne/xacquire. So to make this work a boolean was added the InternalInstruction struct as part of the Prefix state which is set with the added logic in readPrefixes() when decoding an instruction to determine if these prefix bytes are to be disassembled as xacquire or xrelease. Then we let the matcher pick the normal prefix instructionID and we change the Opcode after that when it is set into the MCInst being created. rdar://11019859 llvm-svn: 184490		2013-06-20 22:32:18 +00:00
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hex-immediates.txt
intel-syntax-32.txt
intel-syntax.txt	fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases	2013-04-10 21:52:25 +00:00
invalid-cmp-imm.txt
invalid-VEX-vvvv.txt
lit.local.cfg
marked-up.txt
simple-tests.txt	Update the X86 disassembler to use xacquire and xrelease when appropriate.	2013-06-20 22:32:18 +00:00
truncated-input.txt
x86-32.txt	added basic support for Intel ADX instructions	2013-02-14 19:08:21 +00:00
x86-64.txt	Add CLAC/STAC instruction encoding/decoding support	2013-04-11 04:52:28 +00:00