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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
264 lines
11 KiB
C++
264 lines
11 KiB
C++
//===- AArch64GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines all the static objects used by AArch64RegisterBankInfo.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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namespace llvm {
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RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
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/* StartIdx, Length, RegBank */
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// 0: FPR 16-bit value.
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{0, 16, AArch64::FPRRegBank},
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// 1: FPR 32-bit value.
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{0, 32, AArch64::FPRRegBank},
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// 2: FPR 64-bit value.
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{0, 64, AArch64::FPRRegBank},
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// 3: FPR 128-bit value.
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{0, 128, AArch64::FPRRegBank},
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// 4: FPR 256-bit value.
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{0, 256, AArch64::FPRRegBank},
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// 5: FPR 512-bit value.
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{0, 512, AArch64::FPRRegBank},
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// 6: GPR 32-bit value.
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{0, 32, AArch64::GPRRegBank},
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// 7: GPR 64-bit value.
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{0, 64, AArch64::GPRRegBank},
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};
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// ValueMappings.
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RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
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/* BreakDown, NumBreakDowns */
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// 0: invalid
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{nullptr, 0},
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// 3-operands instructions (all binary operations should end up with one of
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// those mapping).
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// 1: FPR 16-bit value. <-- This must match First3OpsIdx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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// 4: FPR 32-bit value. <-- This must match First3OpsIdx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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// 7: FPR 64-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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// 10: FPR 128-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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// 13: FPR 256-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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// 16: FPR 512-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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// 19: GPR 32-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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// 22: GPR 64-bit value. <-- This must match Last3OpsIdx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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// Cross register bank copies.
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// 25: FPR 16-bit value to GPR 16-bit. <-- This must match
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// FirstCrossRegCpyIdx.
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// Note: This is the kind of copy we see with physical registers.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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// 27: FPR 32-bit value to GPR 32-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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// 29: FPR 64-bit value to GPR 64-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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// 31: FPR 128-bit value to GPR 128-bit value (invalid)
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{nullptr, 1},
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{nullptr, 1},
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// 33: FPR 256-bit value to GPR 256-bit value (invalid)
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{nullptr, 1},
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{nullptr, 1},
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// 35: FPR 512-bit value to GPR 512-bit value (invalid)
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{nullptr, 1},
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{nullptr, 1},
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// 37: GPR 32-bit value to FPR 32-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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// 39: GPR 64-bit value to FPR 64-bit value. <-- This must match
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// LastCrossRegCpyIdx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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// 41: FPExt: 16 to 32. <-- This must match FPExt16To32Idx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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// 43: FPExt: 16 to 32. <-- This must match FPExt16To64Idx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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// 45: FPExt: 32 to 64. <-- This must match FPExt32To64Idx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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// 47: FPExt vector: 64 to 128. <-- This must match FPExt64To128Idx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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};
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bool AArch64GenRegisterBankInfo::checkPartialMap(unsigned Idx,
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unsigned ValStartIdx,
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unsigned ValLength,
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const RegisterBank &RB) {
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const PartialMapping &Map = PartMappings[Idx - PartialMappingIdx::PMI_Min];
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return Map.StartIdx == ValStartIdx && Map.Length == ValLength &&
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Map.RegBank == &RB;
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}
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bool AArch64GenRegisterBankInfo::checkValueMapImpl(unsigned Idx,
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unsigned FirstInBank,
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unsigned Size,
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unsigned Offset) {
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unsigned PartialMapBaseIdx = Idx - PartialMappingIdx::PMI_Min;
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const ValueMapping &Map =
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AArch64GenRegisterBankInfo::getValueMapping((PartialMappingIdx)FirstInBank, Size)[Offset];
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return Map.BreakDown == &PartMappings[PartialMapBaseIdx] &&
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Map.NumBreakDowns == 1;
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}
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bool AArch64GenRegisterBankInfo::checkPartialMappingIdx(
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PartialMappingIdx FirstAlias, PartialMappingIdx LastAlias,
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ArrayRef<PartialMappingIdx> Order) {
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if (Order.front() != FirstAlias)
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return false;
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if (Order.back() != LastAlias)
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return false;
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if (Order.front() > Order.back())
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return false;
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PartialMappingIdx Previous = Order.front();
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bool First = true;
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for (const auto &Current : Order) {
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if (First) {
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First = false;
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continue;
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}
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if (Previous + 1 != Current)
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return false;
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Previous = Current;
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}
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return true;
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}
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unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
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unsigned Size) {
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if (RBIdx == PMI_FirstGPR) {
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if (Size <= 32)
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return 0;
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if (Size <= 64)
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return 1;
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return -1;
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}
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if (RBIdx == PMI_FirstFPR) {
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if (Size <= 16)
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return 0;
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if (Size <= 32)
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return 1;
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if (Size <= 64)
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return 2;
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if (Size <= 128)
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return 3;
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if (Size <= 256)
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return 4;
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if (Size <= 512)
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return 5;
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return -1;
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}
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return -1;
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}
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const RegisterBankInfo::ValueMapping *
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AArch64GenRegisterBankInfo::getValueMapping(PartialMappingIdx RBIdx,
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unsigned Size) {
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assert(RBIdx != PartialMappingIdx::PMI_None && "No mapping needed for that");
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unsigned BaseIdxOffset = getRegBankBaseIdxOffset(RBIdx, Size);
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if (BaseIdxOffset == -1u)
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return &ValMappings[InvalidIdx];
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unsigned ValMappingIdx =
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First3OpsIdx + (RBIdx - PartialMappingIdx::PMI_Min + BaseIdxOffset) *
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ValueMappingIdx::DistanceBetweenRegBanks;
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assert(ValMappingIdx >= First3OpsIdx && ValMappingIdx <= Last3OpsIdx &&
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"Mapping out of bound");
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return &ValMappings[ValMappingIdx];
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}
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AArch64GenRegisterBankInfo::PartialMappingIdx
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AArch64GenRegisterBankInfo::BankIDToCopyMapIdx[]{
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PMI_None, // CCR
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PMI_FirstFPR, // FPR
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PMI_FirstGPR, // GPR
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};
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const RegisterBankInfo::ValueMapping *
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AArch64GenRegisterBankInfo::getCopyMapping(unsigned DstBankID,
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unsigned SrcBankID, unsigned Size) {
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assert(DstBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
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assert(SrcBankID < AArch64::NumRegisterBanks && "Invalid bank ID");
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PartialMappingIdx DstRBIdx = BankIDToCopyMapIdx[DstBankID];
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PartialMappingIdx SrcRBIdx = BankIDToCopyMapIdx[SrcBankID];
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assert(DstRBIdx != PMI_None && "No such mapping");
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assert(SrcRBIdx != PMI_None && "No such mapping");
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if (DstRBIdx == SrcRBIdx)
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return getValueMapping(DstRBIdx, Size);
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assert(Size <= 64 && "GPR cannot handle that size");
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unsigned ValMappingIdx =
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FirstCrossRegCpyIdx +
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(DstRBIdx - PMI_Min + getRegBankBaseIdxOffset(DstRBIdx, Size)) *
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ValueMappingIdx::DistanceBetweenCrossRegCpy;
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assert(ValMappingIdx >= FirstCrossRegCpyIdx &&
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ValMappingIdx <= LastCrossRegCpyIdx && "Mapping out of bound");
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return &ValMappings[ValMappingIdx];
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}
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const RegisterBankInfo::ValueMapping *
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AArch64GenRegisterBankInfo::getFPExtMapping(unsigned DstSize,
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unsigned SrcSize) {
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// We support:
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// - For Scalar:
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// - 16 to 32.
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// - 16 to 64.
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// - 32 to 64.
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// => FPR 16 to FPR 32|64
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// => FPR 32 to FPR 64
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// - For vectors:
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// - v4f16 to v4f32
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// - v2f32 to v2f64
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// => FPR 64 to FPR 128
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// Check that we have been asked sensible sizes.
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if (SrcSize == 16) {
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assert((DstSize == 32 || DstSize == 64) && "Unexpected half extension");
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if (DstSize == 32)
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return &ValMappings[FPExt16To32Idx];
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return &ValMappings[FPExt16To64Idx];
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}
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if (SrcSize == 32) {
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assert(DstSize == 64 && "Unexpected float extension");
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return &ValMappings[FPExt32To64Idx];
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}
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assert((SrcSize == 64 || DstSize == 128) && "Unexpected vector extension");
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return &ValMappings[FPExt64To128Idx];
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}
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} // End llvm namespace.
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