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c168815f4b
Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
52 lines
1.4 KiB
LLVM
52 lines
1.4 KiB
LLVM
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@i = global i64 4294967295, align 8
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@j = global i64 15, align 8
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@ii = global i64 4294967295, align 8
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@k = common global i64 0, align 8
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@l = common global i64 0, align 8
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@m = common global i64 0, align 8
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define void @test1() nounwind {
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entry:
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%0 = load i64, i64* @i, align 8
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%1 = load i64, i64* @j, align 8
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%add = add nsw i64 %1, %0
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store i64 %add, i64* @k, align 8
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move ${{[0-9]+}}, $t8
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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ret void
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}
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define void @test2() nounwind {
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entry:
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%0 = load i64, i64* @i, align 8
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%1 = load i64, i64* @j, align 8
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%sub = sub nsw i64 %0, %1
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; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move ${{[0-9]+}}, $t8
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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store i64 %sub, i64* @l, align 8
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ret void
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}
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define void @test3() nounwind {
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entry:
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%0 = load i64, i64* @ii, align 8
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%add = add nsw i64 %0, 15
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; 16: addiu ${{[0-9]+}}, 15
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; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move ${{[0-9]+}}, $t8
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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store i64 %add, i64* @m, align 8
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ret void
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}
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