mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 11:33:24 +02:00
ac58e2a800
Summary: Without these patterns we would generate a complete LL/SC sequence. This would be problematic for memory regions marked as WRITE-only or READ-only, as the instructions LL/SC would read/write to the protected memory regions correspondingly. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14397 llvm-svn: 252293
27 lines
596 B
LLVM
27 lines
596 B
LLVM
; RUN: llc -asm-show-inst -march=mipsel -mcpu=mips32r6 < %s | \
|
|
; RUN: FileCheck %s -check-prefix=CHK32
|
|
; RUN: llc -asm-show-inst -march=mips64el -mcpu=mips64r6 < %s | \
|
|
; RUN: FileCheck %s -check-prefix=CHK64
|
|
|
|
@a = common global i32 0, align 4
|
|
@b = common global i64 0, align 8
|
|
|
|
|
|
define i32 @ll_sc(i32 signext %x) {
|
|
; CHK32-LABEL: ll_sc
|
|
|
|
;CHK32: LL_R6
|
|
;CHK32: SC_R6
|
|
%1 = atomicrmw add i32* @a, i32 %x monotonic
|
|
ret i32 %1
|
|
}
|
|
|
|
define i64 @lld_scd(i64 signext %x) {
|
|
; CHK64-LABEL: lld_scd
|
|
|
|
;CHK64: LLD_R6
|
|
;CHK64: SCD_R6
|
|
%1 = atomicrmw add i64* @b, i64 %x monotonic
|
|
ret i64 %1
|
|
}
|