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https://github.com/RPCS3/llvm-mirror.git
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69646a28e6
Summary: This patch fixes pr23772 [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80". The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable. To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP). Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations. When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant ) It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt). Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb Reviewed By: efriedma Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70680
69 lines
2.5 KiB
ArmAsm
69 lines
2.5 KiB
ArmAsm
@ RUN: not llvm-mc -triple thumbv7-apple-ios %s -o /dev/null 2>&1 | FileCheck %s
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add sp, r5, #1
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addw sp, r7, #4
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add sp, r3, r2
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add sp, r3, r5, lsl #3
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sub sp, r5, #1
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subw sp, r7, #4
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sub sp, r3, r2
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sub sp, r3, r5, lsl #3
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@CHECK: error: invalid instruction, any one of the following would fix this:
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@CHECK-NEXT: add sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: invalid operand for instruction
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@CHECK-NEXT: add sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
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@CHECK-NEXT: add sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
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@CHECK-NEXT: add sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register sp
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@CHECK-NEXT: add sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: error: invalid instruction, any one of the following would fix this:
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@CHECK-NEXT: addw sp, r7, #4
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
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@CHECK-NEXT: addw sp, r7, #4
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register sp
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@CHECK-NEXT: addw sp, r7, #4
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@CHECK-NEXT: ^
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@CHECK-NEXT: error: source register must be sp if destination is sp
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@CHECK-NEXT: add sp, r3, r2
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@CHECK-NEXT: ^
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@CHECK-NEXT: error: source register must be sp if destination is sp
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@CHECK-NEXT: add sp, r3, r5, lsl #3
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@CHECK-NEXT: ^
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@CHECK-NEXT: error: invalid instruction, any one of the following would fix this:
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@CHECK-NEXT: sub sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: invalid operand for instruction
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@CHECK-NEXT: sub sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
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@CHECK-NEXT: sub sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
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@CHECK-NEXT: sub sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register sp
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@CHECK-NEXT: sub sp, r5, #1
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@CHECK-NEXT: ^
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@CHECK-NEXT: error: invalid instruction, any one of the following would fix this:
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@CHECK-NEXT: subw sp, r7, #4
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register in range [r0, r12] or r14
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@CHECK-NEXT: subw sp, r7, #4
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@CHECK-NEXT: ^
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@CHECK-NEXT: note: operand must be a register sp
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@CHECK-NEXT: subw sp, r7, #4
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@CHECK-NEXT: ^
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@CHECK-NEXT: error: source register must be sp if destination is sp
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@CHECK-NEXT: sub sp, r3, r2
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@CHECK-NEXT: ^
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@CHECK-NEXT: error: source register must be sp if destination is sp
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@CHECK-NEXT: sub sp, r3, r5, lsl #3
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