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llvm-mirror/test/MC/ARM/ldr-pseudo-unpredictable.s
Oliver Stannard dacbc9891d [ARM] Use new assembler diags for ARM
This converts the ARM AsmParser to use the new assembly matcher error
reporting mechanism, which allows errors to be reported for multiple
instruction encodings when it is ambiguous which one the user intended
to use.

By itself this doesn't improve many error messages, because we don't have
diagnostic text for most operand types, but as we add that then this will allow
more of those diagnostic strings to be used when they are relevant.

Differential revision: https://reviews.llvm.org/D31530

llvm-svn: 314779
2017-10-03 10:26:11 +00:00

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1.1 KiB
ArmAsm

@RUN: llvm-mc -triple armv5-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-ARM %s
@RUN: llvm-mc -triple thumbv7-unknown-linux-gnueabi %s 2>&1 | FileCheck --check-prefix=CHECK-T2 %s
@RUN: not llvm-mc -triple thumbv5-unknown-linux-gnueabi %s 2>&1 | FileCheck --check-prefix=CHECK-NONE %s
@RUN: llvm-mc -triple armv5-base-apple-darwin %s | FileCheck --check-prefix=CHECK-DARWIN-ARM %s
@RUN: llvm-mc -triple thumbv7-base-apple-darwin %s 2>&1 | FileCheck --check-prefix=CHECK-DARWIN-T2 %s
@RUN: not llvm-mc -triple thumbv5-base.apple.darwin %s 2>&1 | FileCheck --check-prefix=CHECK-NONE %s
@ We dont't do the transformation for rt = sp or pc
@ as it is unpredictable for many of the MOV encondings
ldr pc, = 0x4
@ CHECK-ARM: ldr pc, .Ltmp[[TMP0:[0-9]+]]
@ CHECK-DARWIN-ARM: ldr pc, Ltmp0
@ CHECK-T2: ldr.w pc, .Ltmp[[TMP0:[0-9]+]]
@ CHECK-DARWIN-T2: ldr.w pc, Ltmp0
@ CHECK-NONE: instruction requires: thumb2
ldr sp, = 0x8
@ CHECK-ARM: ldr sp, .Ltmp[[TMP1:[0-9]+]]
@ CHECK-DARWIN-ARM: ldr sp, Ltmp1
@ CHECK-T2: ldr.w sp, .Ltmp[[TMP1:[0-9]+]]
@ CHECK-DARWIN-T2: ldr.w sp, Ltmp1
@ CHECK-NONE: instruction requires: thumb2