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f5744d66e0
This adds support for the new family of conditional selection / increment / negation instructions; the low-overhead branch instructions (e.g. BF, WLS, DLS); the CLRM instruction to zero a whole list of registers at once; the new VMRS/VMSR and VLDR/VSTR instructions to get data in and out of 8.1-M system registers, particularly including the new VPR register used by MVE vector predication. To support this, we also add a register name 'zr' (used by the CSEL family to force one of the inputs to the constant 0), and operand types for lists of registers that are also allowed to include APSR or VPR (used by CLRM). The VLDR/VSTR instructions also need a new addressing mode. The low-overhead branch instructions exist in their own separate architecture extension, which we treat as enabled by default, but you can say -mattr=-lob or equivalent to turn it off. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Reviewed By: samparker Subscribers: miyuki, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62667 llvm-svn: 363039
99 lines
5.2 KiB
ArmAsm
99 lines
5.2 KiB
ArmAsm
// RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,+mve -show-encoding < %s \
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// RUN: | FileCheck --check-prefix=CHECK %s
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// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-8msecext,+mve -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-NOSEC %s
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// RUN: FileCheck --check-prefix=ERROR-NOSEC < %t %s
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// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,-mve,+vfp2 -show-encoding < %s 2> %t \
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// RUN: | FileCheck --check-prefix=CHECK-NOMVE %s
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// RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s
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// RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+8msecext,+mve,-vfp2 -show-encoding < %s \
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// RUN: | FileCheck --check-prefix=CHECK-NOVFP %s
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// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=-8msecext,-mve,-vfp2 -show-encoding < %s 2> %t
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// RUN: FileCheck --check-prefix=ERROR-NONE < %t %s
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// RUN: not llvm-mc -triple=thumbv8m.main-none-eabi -mattr=+8msecext,+vfp2 -show-encoding < %s 2> %t
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// RUN: FileCheck --check-prefix=ERROR-V8M < %t %s
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// ERROR-V8M: instruction requires: armv8.1m.main
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// ERROR-NONE: instruction requires: fp registers
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// CHECK-NOVFP: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
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// CHECK-NOMVE: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
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// CHECK-NOSEC: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
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// CHECK: vmsr fpscr_nzcvqc, r0 @ encoding: [0xe2,0xee,0x10,0x0a]
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vmsr fpscr_nzcvqc, r0
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// ERROR-V8M: instruction requires: armv8.1m.main
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// ERROR-NONE: instruction requires: fp registers
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// CHECK-NOVFP: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
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// CHECK-NOMVE: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
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// CHECK-NOSEC: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
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// CHECK: vmrs r10, fpscr_nzcvqc @ encoding: [0xf2,0xee,0x10,0xaa]
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vmrs r10, fpscr_nzcvqc
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// ERROR-V8M: instruction requires: armv8.1m.main
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// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
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// CHECK-NOVFP: vmrs r0, fpcxtns @ encoding: [0xfe,0xee,0x10,0x0a]
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// CHECK-NOMVE: vmrs r0, fpcxtns @ encoding: [0xfe,0xee,0x10,0x0a]
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// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
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// CHECK: vmrs r0, fpcxtns @ encoding: [0xfe,0xee,0x10,0x0a]
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vmrs r0, fpcxtns
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// ERROR-V8M: instruction requires: armv8.1m.main
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// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
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// CHECK-NOVFP: vmsr fpcxtns, r10 @ encoding: [0xee,0xee,0x10,0xaa]
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// CHECK-NOMVE: vmsr fpcxtns, r10 @ encoding: [0xee,0xee,0x10,0xaa]
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// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
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// CHECK: vmsr fpcxtns, r10 @ encoding: [0xee,0xee,0x10,0xaa]
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vmsr fpcxtns, r10
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// ERROR-V8M: instruction requires: armv8.1m.main
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// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
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// CHECK-NOVFP: vmsr fpcxts, r5 @ encoding: [0xef,0xee,0x10,0x5a]
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// CHECK-NOMVE: vmsr fpcxts, r5 @ encoding: [0xef,0xee,0x10,0x5a]
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// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
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// CHECK: vmsr fpcxts, r5 @ encoding: [0xef,0xee,0x10,0x5a]
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vmsr fpcxts, r5
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// ERROR-V8M: instruction requires: armv8.1m.main
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// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
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// CHECK-NOVFP: vmrs r3, fpcxtns @ encoding: [0xfe,0xee,0x10,0x3a]
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// CHECK-NOMVE: vmrs r3, fpcxtns @ encoding: [0xfe,0xee,0x10,0x3a]
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// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
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// CHECK: vmrs r3, fpcxtns @ encoding: [0xfe,0xee,0x10,0x3a]
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vmrs r3, fpcxtns
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// ERROR-V8M: instruction requires: armv8.1m.main
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// ERROR-NONE: instruction requires: ARMv8-M Security Extensions
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// CHECK-NOVFP: vmrs r0, fpcxts @ encoding: [0xff,0xee,0x10,0x0a]
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// CHECK-NOMVE: vmrs r0, fpcxts @ encoding: [0xff,0xee,0x10,0x0a]
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// ERROR-NOSEC: instruction requires: ARMv8-M Security Extensions
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// CHECK: vmrs r0, fpcxts @ encoding: [0xff,0xee,0x10,0x0a]
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vmrs r0, fpcxts
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// ERROR-V8M: instruction requires: mve armv8.1m.main
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// ERROR-NONE: instruction requires: mve
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// ERROR-NOMVE: instruction requires: mve
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// CHECK-NOSEC: vmrs r0, vpr @ encoding: [0xfc,0xee,0x10,0x0a]
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// CHECK: vmrs r0, vpr @ encoding: [0xfc,0xee,0x10,0x0a]
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vmrs r0, vpr
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// ERROR-V8M: instruction requires: mve armv8.1m.main
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// ERROR-NONE: instruction requires: mve
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// ERROR-NOMVE: instruction requires: mve
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// CHECK-NOSEC: vmrs r4, p0 @ encoding: [0xfd,0xee,0x10,0x4a]
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// CHECK: vmrs r4, p0 @ encoding: [0xfd,0xee,0x10,0x4a]
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vmrs r4, p0
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// ERROR-V8M: instruction requires: mve armv8.1m.main
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// ERROR-NONE: instruction requires: mve
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// ERROR-NOMVE: instruction requires: mve
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// CHECK-NOSEC: vmsr vpr, r0 @ encoding: [0xec,0xee,0x10,0x0a]
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// CHECK: vmsr vpr, r0 @ encoding: [0xec,0xee,0x10,0x0a]
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vmsr vpr, r0
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// ERROR-V8M: instruction requires: mve armv8.1m.main
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// ERROR-NONE: instruction requires: mve
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// ERROR-NOMVE: instruction requires: mve
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// CHECK-NOSEC: vmsr p0, r4 @ encoding: [0xed,0xee,0x10,0x4a]
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// CHECK: vmsr p0, r4 @ encoding: [0xed,0xee,0x10,0x4a]
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vmsr p0, r4
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