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cc701bcfdc
In the bottom-up selection DAG scheduling, handle two-address instructions that read/write unspillable registers. Treat the entire chain of two-address nodes as a single live range. llvm-svn: 122472
35 lines
1.0 KiB
LLVM
35 lines
1.0 KiB
LLVM
; RUN: llc < %s
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@ok = internal constant [4 x i8] c"%d\0A\00"
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@no = internal constant [4 x i8] c"no\0A\00"
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define i1 @func2(i128 zeroext %v1, i128 zeroext %v2) nounwind {
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entry:
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%t = call {i128, i1} @llvm.uadd.with.overflow.i128(i128 %v1, i128 %v2)
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%sum = extractvalue {i128, i1} %t, 0
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%sum32 = trunc i128 %sum to i32
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%obit = extractvalue {i128, i1} %t, 1
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br i1 %obit, label %carry, label %normal
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normal:
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%t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum32 ) nounwind
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ret i1 true
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carry:
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%t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
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ret i1 false
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}
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declare i32 @printf(i8*, ...) nounwind
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declare {i96, i1} @llvm.sadd.with.overflow.i96(i96, i96)
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declare {i128, i1} @llvm.uadd.with.overflow.i128(i128, i128)
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define i1 @func1(i96 signext %v1, i96 signext %v2) nounwind {
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entry:
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%t = call {i96, i1} @llvm.sadd.with.overflow.i96(i96 %v1, i96 %v2)
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%obit = extractvalue {i96, i1} %t, 1
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ret i1 %obit
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}
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