Ryan Taylor ea6945ae03 [AMDGPU] Fix for branch offset hardware workaround ... Summary: This fixes a hardware bug that makes a branch offset of 0x3f unsafe. This replaces the 32 bit branch with offset 0x3f to a 64 bit instruction that includes the same 32 bit branch and the encoding for a s_nop 0 to follow. The relaxer than modifies the offsets accordingly. Change-Id: I10b7aed99d651f8159401b01bb421f105fa6288e Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63494 llvm-svn: 364451		2019-06-26 17:34:57 +00:00
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AArch64
AMDGPU	[AMDGPU] Fix for branch offset hardware workaround	2019-06-26 17:34:57 +00:00
ARM	[ARM] Handle fixup_arm_pcrel_9 correctly on big-endian targets	2019-06-26 10:48:40 +00:00
AsmParser	Fix a crash with assembler source and -g.	2019-06-21 13:10:19 +00:00
AVR
BPF
COFF	MC: correct the emission of weak aliases in COFF	2019-06-26 01:09:52 +00:00
Disassembler	[ARM] Extra MVE-related testing.	2019-06-25 11:24:42 +00:00
ELF
Hexagon
Lanai
MachO
Mips	[mips] Mark the lwupc instruction as MIPS64 R6 only	2019-06-19 22:08:06 +00:00
MSP430
PowerPC
RISCV	[RISCV] Add pseudo instruction for calls with explicit register	2019-06-26 10:35:58 +00:00
Sparc
SystemZ	[SystemZ] Support vector load/store alignment hints	2019-06-19 14:20:00 +00:00
WebAssembly	[WebAssembly] Implement tail calls and unify tablegen call classes	2019-06-26 16:17:15 +00:00
X86