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506a5c80b2
Summary: Extract the logic for doing reassociations from DAGCombiner::reassociateOps into a helper function DAGCombiner::reassociateOpsCommutative, and use that helper to trigger reassociation on the original operand order, or the commuted operand order. Codegen is not identical since the operand order will be different when doing the reassociations for the commuted case. That causes some unfortunate churn in some test cases. Apart from that this should be NFC. Reviewers: spatel, craig.topper, tstellar Reviewed By: spatel Subscribers: dmgreen, dschuff, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, hiraditya, aheejin, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61199 llvm-svn: 359476
48 lines
1.7 KiB
LLVM
48 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test that the dag combiner can understand that some vector operands are
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; all-zeros and then optimize the logical operations.
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define void @f1(<2 x i64> %a0) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: vlrepg %v0, 0(%r1)
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; CHECK-NEXT: vgbm %v1, 0
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; CHECK-NEXT: vceqg %v2, %v24, %v1
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; CHECK-NEXT: vn %v0, %v0, %v0
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; CHECK-NEXT: vno %v2, %v2, %v2
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; CHECK-NEXT: vceqg %v0, %v0, %v1
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; CHECK-NEXT: vx %v0, %v0, %v2
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; CHECK-NEXT: vnc %v0, %v2, %v0
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; CHECK-NEXT: vlgvf %r0, %v0, 1
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; CHECK-NEXT: tmll %r0, 1
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; CHECK-NEXT: # %bb.1: # %bb15
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bb:
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%tmp = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> zeroinitializer
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br label %bb1
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bb1: ; preds = %bb
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%tmp2 = load i64, i64* undef, align 8
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%tmp3 = insertelement <2 x i64> undef, i64 %tmp2, i32 1
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%tmp4 = icmp ne <2 x i64> %a0, zeroinitializer
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%tmp5 = xor <2 x i1> %tmp4, zeroinitializer
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%tmp6 = xor <2 x i1> zeroinitializer, %tmp5
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%tmp7 = and <2 x i64> %tmp3, %tmp
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%tmp8 = icmp ne <2 x i64> %tmp7, zeroinitializer
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%tmp9 = xor <2 x i1> zeroinitializer, %tmp8
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%tmp10 = icmp ne <2 x i64> %a0, zeroinitializer
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%tmp11 = xor <2 x i1> %tmp10, %tmp9
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%tmp12 = and <2 x i1> %tmp6, %tmp11
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%tmp13 = extractelement <2 x i1> %tmp12, i32 0
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br i1 %tmp13, label %bb14, label %bb15
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bb14: ; preds = %bb1
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store i64 undef, i64* undef, align 8
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br label %bb15
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bb15: ; preds = %bb14, %bb1
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unreachable
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}
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