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1285ec2ae7
a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
199 lines
6.4 KiB
C++
199 lines
6.4 KiB
C++
//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMINSTRUCTIONINFO_H
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#define ARMINSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "ARMRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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/// ARMII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace ARMII {
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enum {
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//===------------------------------------------------------------------===//
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// Instruction Flags.
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//===------------------------------------------------------------------===//
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// This three-bit field describes the addressing mode used. Zero is unused
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// so that we can tell if we forgot to set a value.
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AddrModeMask = 0xf,
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AddrModeNone = 0,
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AddrMode1 = 1,
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AddrMode2 = 2,
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AddrMode3 = 3,
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AddrMode4 = 4,
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AddrMode5 = 5,
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AddrModeT1 = 6,
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AddrModeT2 = 7,
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AddrModeT4 = 8,
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AddrModeTs = 9, // i8 * 4 for pc and sp relative data
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// Size* - Flags to keep track of the size of an instruction.
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SizeShift = 4,
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SizeMask = 7 << SizeShift,
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SizeSpecial = 1, // 0 byte pseudo or special case.
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Size8Bytes = 2,
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Size4Bytes = 3,
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Size2Bytes = 4,
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// IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
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// and store ops
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IndexModeShift = 7,
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IndexModeMask = 3 << IndexModeShift,
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IndexModePre = 1,
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IndexModePost = 2,
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// Opcode
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OpcodeShift = 9,
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OpcodeMask = 0xf << OpcodeShift,
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// Format
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FormShift = 13,
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FormMask = 31 << FormShift,
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// Pseudo instructions
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Pseudo = 1 << FormShift,
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// Multiply instructions
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MulFrm = 2 << FormShift,
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MulSMLAW = 3 << FormShift,
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MulSMULW = 4 << FormShift,
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MulSMLA = 5 << FormShift,
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MulSMUL = 6 << FormShift,
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// Branch instructions
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Branch = 7 << FormShift,
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BranchMisc = 8 << FormShift,
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// Data Processing instructions
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DPRdIm = 9 << FormShift,
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DPRdReg = 10 << FormShift,
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DPRdSoReg = 11 << FormShift,
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DPRdMisc = 12 << FormShift,
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DPRnIm = 13 << FormShift,
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DPRnReg = 14 << FormShift,
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DPRnSoReg = 15 << FormShift,
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DPRIm = 16 << FormShift,
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DPRReg = 17 << FormShift,
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DPRSoReg = 18 << FormShift,
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DPRImS = 19 << FormShift,
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DPRRegS = 20 << FormShift,
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DPRSoRegS = 21 << FormShift,
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// Load and Store
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LdFrm = 22 << FormShift,
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StFrm = 23 << FormShift,
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// Miscellaneous arithmetic instructions
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ArithMisc = 24 << FormShift,
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// Thumb format
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ThumbFrm = 25 << FormShift,
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// VFP format
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VPFFrm = 26 << FormShift,
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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RegRsShift = 8,
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RegRdShift = 12,
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RegRnShift = 16,
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L_BitShift = 20,
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S_BitShift = 20,
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U_BitShift = 23,
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IndexShift = 24,
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I_BitShift = 25
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};
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}
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class ARMInstrInfo : public TargetInstrInfoImpl {
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const ARMRegisterInfo RI;
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public:
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ARMInstrInfo(const ARMSubtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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virtual bool isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg) const;
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virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
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virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables &LV) const;
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond) const;
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
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virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
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// Predication support.
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virtual bool isPredicated(const MachineInstr *MI) const;
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const std::vector<MachineOperand> &Pred) const;
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virtual
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bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
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const std::vector<MachineOperand> &Pred2) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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};
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// Utility routines
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namespace ARM {
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/// GetInstSize - Returns the size of the specified MachineInstr.
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///
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unsigned GetInstSize(MachineInstr *MI);
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/// GetFunctionSize - Returns the size of the specified MachineFunction.
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///
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unsigned GetFunctionSize(MachineFunction &MF);
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}
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}
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#endif
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