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6ee594a265
Summary: Previously there were two separate pseudo instruction for SDWA on VI and on GFX9. Created one pseudo instruction that is union of both of them. Added verifier to check that operands conform either VI or GFX9. Reviewers: dp, arsenm, vpykhtin Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, artem.tamazov Differential Revision: https://reviews.llvm.org/D34026 llvm-svn: 305886
124 lines
4.2 KiB
C++
124 lines
4.2 KiB
C++
//===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Implementation of the TargetInstrInfo class that is common to all
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/// AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#define GET_INSTRMAP_INFO
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#include "AMDGPUGenInstrInfo.inc"
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// Pin the vtable to this file.
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void AMDGPUInstrInfo::anchor() {}
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AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &ST)
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: AMDGPUGenInstrInfo(-1, -1), ST(ST), AMDGPUASI(ST.getAMDGPUAS()) {}
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// FIXME: This behaves strangely. If, for example, you have 32 load + stores,
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// the first 16 loads will be interleaved with the stores, and the next 16 will
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// be clustered as expected. It should really split into 2 16 store batches.
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//
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// Loads are clustered until this returns false, rather than trying to schedule
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// groups of stores. This also means we have to deal with saying different
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// address space loads should be clustered, and ones which might cause bank
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// conflicts.
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//
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// This might be deprecated so it might not be worth that much effort to fix.
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bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,
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int64_t Offset0, int64_t Offset1,
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unsigned NumLoads) const {
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assert(Offset1 > Offset0 &&
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"Second offset should be larger than first offset!");
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// If we have less than 16 loads in a row, and the offsets are within 64
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// bytes, then schedule together.
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// A cacheline is 64 bytes (for global memory).
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return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
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}
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int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
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switch (Channels) {
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default: return Opcode;
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case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
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case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
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case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
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}
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}
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// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
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enum SIEncodingFamily {
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SI = 0,
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VI = 1,
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SDWA = 2,
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SDWA9 = 3
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};
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// Wrapper for Tablegen'd function. enum Subtarget is not defined in any
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// header files, so we need to wrap it in a function that takes unsigned
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// instead.
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namespace llvm {
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namespace AMDGPU {
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static int getMCOpcode(uint16_t Opcode, unsigned Gen) {
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return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
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}
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}
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}
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static SIEncodingFamily subtargetEncodingFamily(const AMDGPUSubtarget &ST) {
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switch (ST.getGeneration()) {
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case AMDGPUSubtarget::SOUTHERN_ISLANDS:
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case AMDGPUSubtarget::SEA_ISLANDS:
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return SIEncodingFamily::SI;
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case AMDGPUSubtarget::VOLCANIC_ISLANDS:
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case AMDGPUSubtarget::GFX9:
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return SIEncodingFamily::VI;
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// FIXME: This should never be called for r600 GPUs.
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case AMDGPUSubtarget::R600:
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case AMDGPUSubtarget::R700:
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case AMDGPUSubtarget::EVERGREEN:
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case AMDGPUSubtarget::NORTHERN_ISLANDS:
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return SIEncodingFamily::SI;
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}
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llvm_unreachable("Unknown subtarget generation!");
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}
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int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {
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SIEncodingFamily Gen = subtargetEncodingFamily(ST);
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if (get(Opcode).TSFlags & SIInstrFlags::SDWA)
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Gen = ST.getGeneration() == AMDGPUSubtarget::GFX9 ? SIEncodingFamily::SDWA9
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: SIEncodingFamily::SDWA;
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int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
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// -1 means that Opcode is already a native instruction.
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if (MCOp == -1)
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return Opcode;
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// (uint16_t)-1 means that Opcode is a pseudo instruction that has
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// no encoding in the given subtarget generation.
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if (MCOp == (uint16_t)-1)
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return -1;
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return MCOp;
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}
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