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69b2d0adeb
This makes it possible to distinguish between mesa shaders and other kernels even in the presence of compute shaders. Patch By: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Differential Revision: http://reviews.llvm.org/D18559 llvm-svn: 265589
95 lines
4.6 KiB
LLVM
95 lines
4.6 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde | FileCheck %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s
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; CHECK-LABEL: {{^}}v1:
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; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xd
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define amdgpu_ps void @v1(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%2 = extractelement <4 x float> %1, i32 0
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%3 = extractelement <4 x float> %1, i32 2
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%4 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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ret void
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}
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; CHECK-LABEL: {{^}}v2:
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; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xb
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define amdgpu_ps void @v2(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%2 = extractelement <4 x float> %1, i32 0
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%3 = extractelement <4 x float> %1, i32 1
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%4 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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ret void
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}
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; CHECK-LABEL: {{^}}v3:
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; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xe
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define amdgpu_ps void @v3(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%2 = extractelement <4 x float> %1, i32 1
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%3 = extractelement <4 x float> %1, i32 2
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%4 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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ret void
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}
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; CHECK-LABEL: {{^}}v4:
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; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x7
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define amdgpu_ps void @v4(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%2 = extractelement <4 x float> %1, i32 0
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%3 = extractelement <4 x float> %1, i32 1
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%4 = extractelement <4 x float> %1, i32 2
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4)
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ret void
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}
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; CHECK-LABEL: {{^}}v5:
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; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xa
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define amdgpu_ps void @v5(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%2 = extractelement <4 x float> %1, i32 1
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%3 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
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ret void
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}
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; CHECK-LABEL: {{^}}v6:
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; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x6
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define amdgpu_ps void @v6(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%2 = extractelement <4 x float> %1, i32 1
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%3 = extractelement <4 x float> %1, i32 2
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
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ret void
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}
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; CHECK-LABEL: {{^}}v7:
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; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x9
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define amdgpu_ps void @v7(i32 %a1) {
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entry:
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%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
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%1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%2 = extractelement <4 x float> %1, i32 0
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%3 = extractelement <4 x float> %1, i32 3
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3)
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ret void
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}
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declare <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) readnone
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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